公开(公告)号：US09661707B2

公开(公告)日：2017-05-23

申请号：US15138739

申请日：2016-04-26

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/66 ,  H05B33/08 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L27/092

CPC classification number: H05B33/083 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/78

Abstract: A semiconductor device includes first and second field effect transistors (FETs) formed in a semiconductor substrate having a first main surface. The first FET includes first source and drain contact grooves, each running in a first direction parallel to the first main surface, each formed in the first main surface. First source regions are electrically connected to a conductive material in the first source contact groove. First drain regions are electrically connected to a conductive material in the first drain contact groove. The second FET includes second source and drain contact grooves, each running in a second direction parallel to the first main surface, each formed in the first main surface. Second source regions are electrically connected to a conductive material in the second source contact groove, and second drain regions are electrically connected to a conductive material in the second drain contact groove.

公开(公告)号：US09614033B2

公开(公告)日：2017-04-04

申请号：US14977393

申请日：2015-12-21

Applicant: Infineon Technologies AG

Inventor： Christoph Kadow ,  Till Schloesser

IPC: H01L29/06 ,  H01L21/78 ,  H01L21/762 ,  H01L29/78 ,  H01L21/308 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L29/0649 ,  H01L21/308 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/78 ,  H01L29/045 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/1033 ,  H01L29/407 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/78

Abstract: An embodiment of a semiconductor device comprises a first load terminal contact area at a first side of a semiconductor body. A second load terminal contact area is at a second side of the semiconductor body opposite to the first side. A control terminal contact area is at the second side of the semiconductor body. An isolation structure extends through the semiconductor body between the first and second sides. The isolation structure electrically isolates a first part of the semiconductor body from a second part of the semiconductor body. A first thickness of the first part of the semiconductor body is smaller than a second thickness of the second part of the semiconductor body.

公开(公告)号：US09614032B2

公开(公告)日：2017-04-04

申请号：US15081423

申请日：2016-03-25

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/45 ,  H01L21/265 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/0634 ,  H01L21/26586 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1008 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825

Abstract: A semiconductor device comprises a transistor in a semiconductor body having a first main surface and a second main surface, the first main surface being opposite to the second main surface. The transistor comprises a source region at the first main surface, a drain region, a body region, a drift zone, and a gate electrode at the body region. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The gate electrode is disposed in trenches extending in the first direction. The transistor further comprises an insulating layer adjacent to the second main surface of the body region. The source region vertically extends to the second main surface.

公开(公告)号：US20160365443A1

公开(公告)日：2016-12-15

申请号：US15182120

申请日：2016-06-14

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7819 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

Abstract: A transistor cell includes a drift region, a source region, a body region, and a drain region that is laterally spaced apart from the source region. A gate electrode is adjacent the body region. A field electrode is arranged in the drift region. A source electrode is connected to the source region and the body region, and a drain electrode is connected to the drain region. An avalanche bypass structure is coupled between the source electrode and the drain electrode and includes a first semiconductor layer of the first doping type, a second semiconductor layer of the first doping type, and a pn-junction arranged between the first semiconductor layer and the source electrode. The second semiconductor layer has a higher doping concentration than the first semiconductor layer and is arranged between the second semiconductor layer and the drift region. The drain electrode is electrically connected to the second semiconductor layer.

Abstract translation: 晶体管单元包括与源极区域横向间隔开的漂移区域，源极区域，体区域和漏极区域。 栅电极与身体区域相邻。 场漂移区域设置场电极。 源电极连接到源极区域和主体区域，并且漏电极连接到漏极区域。 雪崩旁路结构耦合在源电极和漏极之间，并且包括第一掺杂型的第一半导体层，第一掺杂型的第二半导体层和布置在第一半导体层和源极之间的pn结 电极。 第二半导体层具有比第一半导体层更高的掺杂浓度，并且布置在第二半导体层和漂移区之间。 漏极电连接到第二半导体层。

公开(公告)号：US20160190256A1

公开(公告)日：2016-06-30

申请号：US15062370

申请日：2016-03-07

Applicant: Infineon Technologies AG

Inventor： Martin Vielemeyer ,  Andreas Meiser ,  Till Schloesser ,  Franz Hirler ,  Martin Poelzl

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7825

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.

Abstract translation: 半导体器件包括具有主表面的半导体衬底中的晶体管。 晶体管包括源极区，漏极区，沟道区，漂移区，栅电极和与栅电极相邻的栅极电介质。 栅电极设置成与沟道区域的至少两侧相邻。 沟道区域和漂移区域沿着平行于源极区域和漏极区域之间的主表面的第一方向设置。 栅极电介质具有在栅电极的不同位置处变化的厚度。

公开(公告)号：US20160190241A1

公开(公告)日：2016-06-30

申请号：US14977393

申请日：2015-12-21

Applicant: Infineon Technologies AG

Inventor： Christoph Kadow ,  Till Schloesser

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/78 ,  H01L21/762 ,  H01L21/308 ,  H01L29/45 ,  H01L29/10

CPC classification number: H01L29/0649 ,  H01L21/308 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/78 ,  H01L29/045 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/1033 ,  H01L29/407 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/78

Abstract: An embodiment of a semiconductor device comprises a first load terminal contact area at a first side of a semiconductor body. A second load terminal contact area is at a second side of the semiconductor body opposite to the first side. A control terminal contact area is at the second side of the semiconductor body. An isolation structure extends through the semiconductor body between the first and second sides. The isolation structure electrically isolates a first part of the semiconductor body from a second part of the semiconductor body. A first thickness of the first part of the semiconductor body is smaller than a second thickness of the second part of the semiconductor body.

Abstract translation: 半导体器件的实施例包括在半导体本体的第一侧的第一负载端子接触区域。 第二负载端子接触区域位于半导体本体的与第一侧相对的第二侧。 控制端子接触区域位于半导体本体的第二侧。 隔离结构在第一和第二侧之间延伸穿过半导体本体。 隔离结构将半导体本体的第一部分与半导体本体的第二部分电隔离。 半导体本体的第一部分的第一厚度小于半导体本体的第二部分的第二厚度。

公开(公告)号：US09324829B2

公开(公告)日：2016-04-26

申请号：US13850037

申请日：2013-03-25

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Markus Zundel

IPC: H01L21/336 ,  H01L29/66 ,  H01L23/48 ,  H01L29/423 ,  H01L21/768 ,  H01L29/739 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/66477 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a trench extending from a first surface of a semiconductor body into the semiconductor body such that a first trench section and at least one second trench section adjoin the first trench section, wherein the first trench section is wider than the second trench section. A first electrode is formed, in the at least one second trench section, and dielectrically insulated from semiconductor regions of the semiconductor body by a first dielectric layer. An inter-electrode dielectric layer is formed, in the at least one second trench section, on the first electrode. A second electrode is formed, in the at least one second trench section on the inter-electrode dielectric layer, and in the first trench section, such that the second electrode at least in the first trench section is dielectrically insulated from the semiconductor body by a second dielectric layer.

Abstract translation: 一种方法包括形成从半导体主体的第一表面延伸到半导体本体中的沟槽，使得第一沟槽部分和与第一沟槽部分相邻的至少一个第二沟槽部分，其中第一沟槽部分比第二沟槽部分宽 。 第一电极在至少一个第二沟槽部分中形成，并且通过第一介电层与半导体本体的半导体区域介电绝缘。 在至少一个第二沟槽部分中，在第一电极上形成电极间电介质层。 第二电极形成在电极间电介质层的至少一个第二沟槽部分中，并且在第一沟槽部分中，使得至少在第一沟槽部分中的第二电极与半导体本体电介质绝缘 第二电介质层。

公开(公告)号：US20150333058A1

公开(公告)日：2015-11-19

申请号：US14813738

申请日：2015-07-30

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Markus Zundel ,  Till Schloesser

IPC: H01L27/08 ,  H01L21/768 ,  H01L29/40 ,  H01L49/02

CPC classification number: H01L27/0805 ,  H01L21/7687 ,  H01L21/76877 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L28/90 ,  H01L29/407

Abstract: A semiconductor device in a semiconductor substrate includes a trench in a first main surface of the semiconductor substrate. The trench includes a first trench portion extending in a first direction and a second trench portion extending in the first direction. The first trench portion is connected with the second trench portion in a lateral direction. The first trench portion and the second trench portion are arranged one after the other along the first direction. The semiconductor device further includes a trench conductive structure having a conductive material disposed in the first trench portion, and a trench capacitor structure having a capacitor dielectric and a first capacitor electrode disposed in the second trench portion. The first capacitor electrode includes a layer lining a sidewall of the second trench portion.

Abstract translation: 半导体衬底中的半导体器件包括在半导体衬底的第一主表面中的沟槽。 沟槽包括沿第一方向延伸的第一沟槽部分和沿第一方向延伸的第二沟槽部分。 第一沟槽部分沿横向方向与第二沟槽部分连接。 第一沟槽部分和第二沟槽部分沿着第一方向一个接一个布置。 半导体器件还包括具有设置在第一沟槽部分中的导电材料的沟槽导电结构，以及具有电容器电介质的沟槽电容器结构和设置在第二沟槽部分中的第一电容器电极。 第一电容器电极包括衬在第二沟槽部分的侧壁上的层。

公开(公告)号：US09123801B2

公开(公告)日：2015-09-01

申请号：US14027570

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Thorsten Meyer

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66704 ,  H01L21/28008 ,  H01L21/76 ,  H01L21/761 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7835

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. The semiconductor device further includes a conductive layer beneath the gate electrode and insulated from the gate electrode.

Abstract translation: 半导体器件包括具有第一主表面的半导体衬底中的晶体管。 晶体管包括源极区域，漏极区域，沟道区域，漂移区域和与沟道区域的至少两侧相邻的栅电极。 沟道区域和漂移区沿着平行于第一主表面的第一方向，在源极区域和漏极区域之间设置。 半导体器件还包括在栅电极下方并与栅电极绝缘的导电层。

公开(公告)号：US20150076590A1

公开(公告)日：2015-03-19

申请号：US14027570

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Thorsten Meyer

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66704 ,  H01L21/28008 ,  H01L21/76 ,  H01L21/761 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7835

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. The semiconductor device further includes a conductive layer beneath the gate electrode and insulated from the gate electrode.

Abstract translation: 半导体器件包括具有第一主表面的半导体衬底中的晶体管。 晶体管包括源极区域，漏极区域，沟道区域，漂移区域和与沟道区域的至少两侧相邻的栅电极。 沟道区域和漂移区沿着平行于第一主表面的第一方向，在源极区域和漏极区域之间设置。 半导体器件还包括在栅电极下方并与栅电极绝缘的导电层。