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    Techniques for generating a PAM eye diagram in a receiver
    62.
    发明授权
    Techniques for generating a PAM eye diagram in a receiver 有权

    公开(公告)号：US12003352B2

    公开(公告)日：2024-06-04

    申请号：US17029445

    申请日：2020-09-23

    Applicant: Intel Corporation

    Inventor： Peng Li ,  Masashi Shimanouchi ,  Hsinho Wu

    IPC: H04L25/03 ,  H03M1/12 ,  H04B10/54 ,  H04B10/69 ,  H04L27/01

    CPC classification number: H04L25/03031 ,  H03M1/1215 ,  H04B10/541 ,  H04B10/6971 ,  H04L25/03267 ,  H04L27/01 ,  H04L2025/0349

    Abstract: A method facilitates determining transmission loss in a transmission signal and adjusting a receiver setting of a receiver to compensate for the transmission loss. The method includes transmitting a transmission signal from a transmitter and receiving the transmission signal by a first receiver and a second receiver. The method includes digitizing the transmission signal by the first receiver at a first sampling frequency and digitizing the transmission signal by the second receiver at a second sampling frequency that is less than or equal to the first sampling frequency. The method includes generating a PAM-n eye diagram of the transmission signal by the second receiver using digitized signals digitized by the first and second receivers and adjusting an equalizer setting of a first equalizer of the first receiver using eye-opening information of the PAM-n eye diagram where the eye-opening information includes information for the transmission loss.

    Data loss prevention for integrated memory buffer of a self encrypting drive
    65.
    发明授权
    Data loss prevention for integrated memory buffer of a self encrypting drive 有权

    公开(公告)号：US10929251B2

    公开(公告)日：2021-02-23

    申请号：US16370644

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Peng Li ,  David J. Pelster ,  Gamil Cain ,  Ryan J. Norton

    IPC: G06F11/00 ,  G06F11/14 ,  G06F3/06 ,  G06F11/30 ,  G06F12/14

    Abstract: A solid state drive (SSD) includes a nonvolatile memory array and a cache memory. The nonvolatile memory array has an encrypted integrated memory buffer (IMB) space. The cache memory has a decrypted copy of the IMB and an encrypted backup copy of the IMB. In power loss recovery (PLR) after a power loss imminent (PLI) event, the SSD can determine whether to recover the unencrypted copy of the IMB or the backup encrypted copy. The backup encrypted copy can reduce the risk of loss of data in the IMB in the event that multiple PLI events occur and a corrupted copy of the IMB is used to overwrite the IMB in the nonvolatile memory during a previous PLR.

    Update-insert for key-value storage interface
    66.
    发明授权
    Update-insert for key-value storage interface 有权

    公开(公告)号：US10831734B2

    公开(公告)日：2020-11-10

    申请号：US15973428

    申请日：2018-05-07

    Applicant: Intel Corporation

    Inventor： Peng Li ,  Sanjeev N. Trika

    IPC: G06F16/00 ,  G06F16/22 ,  G06F16/25 ,  G06F16/23

    Abstract: An update-insert (“upsert”) interface manages updates to key-value storage at a memory or storage device. An upsert token is used to store a key and data for a transform to update a previous value stored for a key-value pair. The upsert token processing includes an upsert command to generate the upsert token for an existing key-value pair and store the upsert token in one or more first non-volatile memory (NVM) devices maintained at a memory or storage device. A hash-to-physical (H2P) table or index stored in one or more second NVM devices of the memory or storage device is utilized to locate and read the data for the key and the data for the transform and coalesce the transform(s) into a current value for the key-value pair, thereby avoiding unnecessary read and write amplification when updating key-value storage.

    CONCEPT FOR STORING FILE SYSTEM METADATA WITHIN SOLID-STAGE STORAGE DEVICES
    67.
    发明申请
    CONCEPT FOR STORING FILE SYSTEM METADATA WITHIN SOLID-STAGE STORAGE DEVICES 审中-公开

    公开(公告)号：US20190235779A1

    公开(公告)日：2019-08-01

    申请号：US16378606

    申请日：2019-04-09

    Applicant: Intel Corporation

    Inventor： Peng Li

    IPC: G06F3/06 ,  G06F16/14

    CPC classification number: G06F3/0643 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0673 ,  G06F16/14

    Abstract: Examples relate to a controller apparatus or controller device for a solid-stage storage device, to an apparatus or device for a host computer, to corresponding methods and computer programs, to a solid-stage storage device and to a host computer comprising a solid-state storage device. Examples provide a controller apparatus for a solid-state storage device. The solid-state storage device comprises non-volatile buffer memory circuitry and storage circuitry. The controller apparatus comprises interface circuitry for communicating with a host computer. The controller apparatus comprises processing circuitry configured to obtain a control instruction related to a file system of a partition from the host computer. The partition is at least partially stored within the storage circuitry of the solid-state storage device. The control instruction indicates a location of file system metadata within the partition. The processing circuitry is configured to store the file system metadata within the non-volatile buffer memory circuitry of the solid-state storage device based on the location of the file system metadata.

    Programmable photonic-electronic integrated circuit for optical testing
    68.
    发明授权
    Programmable photonic-electronic integrated circuit for optical testing 有权

    公开(公告)号：US10236975B2

    公开(公告)日：2019-03-19

    申请号：US15430053

    申请日：2017-02-10

    Applicant: INTEL CORPORATION

    Inventor： Peng Li

    IPC: H04B10/077 ,  H04B10/079 ,  H04B10/073 ,  H04B10/071 ,  H04B10/40

    Abstract: The present disclosure provides a programmable integrated circuit die for optical testing. The integrated circuit die includes both photonic and electronic elements. In particular, the integrated circuit die may include a memory block, a programmable logic block (for example, a field programmable gate array), an electrical transceiver block, an optical transceiver block, and an optical test interface unit. The programmable logic block may be programmed to have logic functionalities of an embedded microcontroller and of various encoders/decoders. The logic functions may be soft, hard, or mixed. The memory may be used to store test patterns, look-up tables, measured waveforms, error time profiles and statistics. The electrical and optical transceivers may implement PAMn, NRZ, or QAMn modulations and may have programmable parameters, including: voltage levels; optical power; slew rate; magnitude/phase; clock generation and recovery; equalizations; sampling levels; and sampling times. Other embodiments and features are also disclosed.

    DATA MANAGEMENT SYSTEM EMPLOYING A HASH-BASED AND TREE-BASED KEY-VALUE DATA STRUCTURE
    70.
    发明申请
    DATA MANAGEMENT SYSTEM EMPLOYING A HASH-BASED AND TREE-BASED KEY-VALUE DATA STRUCTURE 审中-公开

    公开(公告)号：US20190034427A1

    公开(公告)日：2019-01-31

    申请号：US15856686

    申请日：2017-12-28

    Applicant: Intel Corporation

    Inventor： Sanjeev N. Trika ,  Dongchul Park ,  Peng Li ,  Francis R. Corrado ,  Robert A. Dickinson

    IPC: G06F17/30

    Abstract: Disclosed is a data management system configured to provide a key-value data structure architecture for use with a storage device. The key-value data structure includes a logic tree having a tree-based index and a hash table having a hash-based index. For a ‘scan’ (or range query) operation, the data management system scans the tree-based index to determine which keys exist between two search keys in the tree-based index. For a ‘get’ (e.g., a value request) operation, the data management system applies a hash function to a provided key to determine an index in the hash table by which to retrieve a value that corresponds with the provided key. Other operations (e.g., ‘put’, ‘update’, ‘delete’) may include updating both the tree-based index and the hash-based index. The logic tree stores keys and stores a zero byte-sized value with each of the keys, to limit the size of the logic tree.

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