公开(公告)号：US20060178852A1

公开(公告)日：2006-08-10

申请号：US11052491

申请日：2005-02-04

申请人： Charles Johns ,  Michael Wang

发明人： Charles Johns ,  Michael Wang

IPC分类号： G01K1/00

CPC分类号： G01K7/015 ,  G01K2219/00

摘要： A method, computer program product, and apparatus for obtaining a digital temperature reading from within an integrated circuit. In a preferred embodiment, a temperature-stable constant current source is applied to a tapped series of resistors to obtain a set of stable reference voltages. These reference voltages are fed into an analog multiplexer, which selects a single reference voltage to output to a comparator. A PTAT (proportional to absolute temperature) voltage signal is also applied to the comparator, so that the output of the comparator indicates a comparison between the selected reference voltage and the PTAT signal. A digital temperature reading is obtained by using finite-state control to apply test values to the multiplexer in order to search for a value corresponding to a reference voltage that is closest to the value of the PTAT signal. The value that is found is a digital representation of the temperature.

摘要翻译： 一种用于从集成电路内获得数字温度读数的方法，计算机程序产品和装置。 在优选实施例中，将温度稳定的恒流源施加到抽头的一系列电阻器以获得一组稳定的参​​考电压。 这些参考电压被馈送到模拟多路复用器中，其选择单个参考电压以输出到比较器。 比较器也施加PTAT（与绝对温度成比例）的电压信号，使得比较器的输出指示所选择的参考电压和PTAT信号之间的比较。 通过使用有限状态控制将测试值应用于多路复用器来获得数字温度读数，以便搜索与最接近PTAT信号值的参考电压相对应的值。 找到的值是温度的数字表示。

公开(公告)号：US20060155955A1

公开(公告)日：2006-07-13

申请号：US11032194

申请日：2005-01-10

申请人： Michael Gschwind ,  Charles Johns ,  Harm Hofstee ,  James Kahle

发明人： Michael Gschwind ,  Charles Johns ,  Harm Hofstee ,  James Kahle

IPC分类号： G06F15/00

CPC分类号： G06F15/8007 ,  G06F13/1663

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。

公开(公告)号：US20060097757A1

公开(公告)日：2006-05-11

申请号：US10982019

申请日：2004-11-05

申请人： Melia Gordon ,  Charles Johns ,  Hiroki Kihara ,  Iwao Takiguchi ,  Tetsuji Tamura ,  Michael Wang ,  Kazuaki Yazawa ,  Munehiro Yoshida

发明人： Melia Gordon ,  Charles Johns ,  Hiroki Kihara ,  Iwao Takiguchi ,  Tetsuji Tamura ,  Michael Wang ,  Kazuaki Yazawa ,  Munehiro Yoshida

IPC分类号： H03K5/153

CPC分类号： G01K15/00 ,  G01R31/2856 ,  G01R31/2874 ,  G01R31/31704 ,  G01R31/319 ,  G01R31/31908

摘要： An integrated circuit die is disclosed including a temperature detection circuit and a memory configured to store calibration data. The temperature detection circuit is operatively coupled to the memory, and receives an input signal. The temperature detection circuit is configured to produce an output signal dependent upon the input signal and indicative of whether a temperature of the integrated circuit die is greater than a selected temperature. During a normal operating mode of the integrated circuit die the input signal comprises the calibration data. A system and methods for calibrating the temperature detection circuit are also described.

公开(公告)号：US20060095669A1

公开(公告)日：2006-05-04

申请号：US10976263

申请日：2004-10-28

申请人： Michael Day ,  Charles Johns ,  Thuong Truong

发明人： Michael Day ,  Charles Johns ,  Thuong Truong

IPC分类号： G06F12/14

CPC分类号： G06F12/0848 ,  G06F12/0875

摘要： The present invention provides a method of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. In an embodiment of the invention, a processor can write data to the cache or other fast memory without also writing it to main memory. The portion of the cache or other fast memory can be used as additional system memory.

摘要翻译： 本发明提供一种将从I / O设备，网络或盘传送的数据存储到高速缓存或其他快速存储器的一部分中的方法，而不将其写入主存储器。 此外，数据被“锁定”到高速缓存或其他快速存储器中，直到它被加载使用为止。 数据保留在锁定缓存中，直到它在软件控制下被特别覆盖为止。 在本发明的一个实施例中，处理器可以将数据写入高速缓存或其它快速存储器，而不将其写入主存储器。 高速缓存或其他快速存储器的部分可以用作额外的系统存储器。

公开(公告)号：US20060031835A1

公开(公告)日：2006-02-09

申请号：US10912479

申请日：2004-08-05

申请人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle

发明人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle

IPC分类号： G06F9/46

CPC分类号： G06F1/3203

摘要： The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.

摘要翻译： 本发明提供用于控制元件的功耗。 第一个功率控制命令由该元件的软件发出。 确定功率控制命令是否对应于由硬件定义的该元件的容许功率控制状态。 如果功率控制命令不是该元件的允许功率控制状态，则硬件将功率控制设置在比由软件发出的功率控制状态更高的水平。 通过软件为芯片的不同元件定义功耗层级，其通过芯片上的任何元件或子元件提供最低功耗水平。

公开(公告)号：US20050216610A1

公开(公告)日：2005-09-29

申请号：US10809553

申请日：2004-03-25

申请人： Charles Johns ,  James Kahle ,  Peichun Liu ,  Thuong Truong

发明人： Charles Johns ,  James Kahle ,  Peichun Liu ,  Thuong Truong

IPC分类号： G06F12/08 ,  G06F13/28

CPC分类号： G06F13/28 ,  G06F12/0835 ,  G06F12/0837 ,  G06F12/0862

摘要： The present invention provides a method and a system for providing cache management commands in a system supporting a DMA mechanism and caches. A DMA mechanism is set up by a processor. Software running on the processor generates cache management commands. The DMA mechanism carries out the commands, thereby enabling the software program management of the caches. The commands include commands for writing data to the cache, loading data from the cache, and for marking data in the cache as no longer needed. The cache can be a system cache or a DMA cache.

摘要翻译： 本发明提供了一种用于在支持DMA机制和高速缓存的系统中提供高速缓存管理命令的方法和系统。 DMA机制由处理器设置。 处理器上运行的软件会生成缓存管理命令。 DMA机制执行命令，从而实现高速缓存的软件程序管理。 这些命令包括用于将数据写入缓存的命令，从高速缓存加载数据，以及用于在不再需要的情况下将数据标记在缓存中。 缓存可以是系统缓存或DMA高速缓存。

公开(公告)号：US20050160239A1

公开(公告)日：2005-07-21

申请号：US10759939

申请日：2004-01-16

申请人： Charles Johns

发明人： Charles Johns

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0835 ,  G06F12/0831 ,  G06F12/0879

摘要： In a multiprocessor system, comprising master and slave processors, a cache coherency controller, and address concentration devices; a method for improving coherent data transfers is described. A command transaction is generated, and a subsequent command from an initiator. Tags added to the responses or further request responses, stream on high-speed busses. Snoops and accumulated snoops expand on cacheline requests as each processor separates burst commands into multiple cacheline requests. Address concentrators containing a cacheline queue function, funnel transaction requests to a global serialization device, where a queuing process prioritizes indicia and coordinates the results among the processors. The cache issues a single burst command for each affected line. System coherency, performance, and latency improvements occur. Additional support for burst transfers between coherent processors is provided.

摘要翻译： 在多处理器系统中，包括主处理器和从属处理器，高速缓存一致性控制器和地址集中器件; 描述了一种改进相干数据传输的方法。 生成命令事务，以及来自启动器的后续命令。 标签添加到响应或进一步请求响应，流在高速公交车。 每个处理器将突发命令分离为多个缓存线请求时，侦听和累积侦听器会扩展缓存引用请求。 包含缓存线队列功能的地址集中器，向全局序列化设备发送流量事务请求，其中排队过程优先处理标记并在处理器之间协调结果。 缓存为每个受影响的线路发出单个突发命令。 发生系统一致性，性能和延迟改进。 提供对相干处理器之间的突发传输的额外支持。

公开(公告)号：US20050111354A1

公开(公告)日：2005-05-26

申请号：US10718302

申请日：2003-11-20

申请人： Shigehiro Asano ,  Charles Johns ,  Matthew King ,  Peichun Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Johns ,  Matthew King ,  Peichun Liu ,  David Mui ,  Jieming Qi

IPC分类号： H04L12/24 ,  H04L12/26

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。

公开(公告)号：US20050097280A1

公开(公告)日：2005-05-05

申请号：US10697897

申请日：2003-10-30

申请人： Harm Hofstee ,  Charles Johns ,  James Kahle

发明人： Harm Hofstee ,  Charles Johns ,  James Kahle

IPC分类号： G06F12/00 ,  G06F12/10

CPC分类号： G06F12/0284 ,  G06F13/1652

摘要： A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.

摘要翻译： 提出了一种用于通过异构处理器共享存储器的系统，每个处理器适于处理其自身的指令集。 公共总线用于将公共存储器耦合到各种处理器。 在一个实施例中，用于多于一个处理器的高速缓存存储在共享存储器中。 在另一个实施例中，一些处理器包括映射到共享存储器池的本地存储器区域。 在另一个实施例中，包括在一个或多个处理器中的本地存储器被部分地共享，使得一些本地存储器被映射到共享存储器区域，而本地存储器中的剩余存储器对于特定处理器是专用的。

公开(公告)号：US20050097231A1

公开(公告)日：2005-05-05

申请号：US10697903

申请日：2003-10-30

申请人： Harm Hofstee ,  Charles Johns ,  James Kahle

发明人： Harm Hofstee ,  Charles Johns ,  James Kahle

IPC分类号： G06F3/00 ,  G06F3/14 ,  G09G5/14

CPC分类号： G06F3/1423 ,  G06F3/1454 ,  G09G5/14 ,  G09G2360/121 ,  G09G2370/04

摘要： A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.

摘要翻译： 灵活的输入/输出控制器逻辑与现有的输入/输出控制器（IOC）进行接口，以便配置向国际奥委会发送和接收的数据量。 灵活的I / O接口以特定组件确定的速率从组件接收数据。 然后，灵活的I / O接口以适合于I / O控制器的速率将接收的数据馈送到传统的I / O控制器。 因此，保持与各个I / O控制器的接口。 灵活的I / O逻辑平衡多个独立I / O控制器之间的带宽，以便更好地利用整个系统I / O带宽。 在一个实施例中，在系统构建期间确定由灵活I / O逻辑管理的I / O配置，而在另一实施例中，在系统初始化期间设置I / O配置。