公开(公告)号：US6049484A

公开(公告)日：2000-04-11

申请号：US150907

申请日：1998-09-10

Applicant: Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

Inventor： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14

Abstract: A method to erase data from a flash EEPROM is disclosed. Electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by erasing the flash EEPROM cell by first applying a high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a ground reference potential is applied to the semiconductor substrate and the control gate. At this same time the drain is floating. Floating the source and drain and applying the ground reference potential to the semiconductor substrate then detraps the flash EEPROM cell. At the same time, a relatively large negative voltage pulse is applied to the control gate.

Abstract translation: 公开了一种从闪存EEPROM擦除数据的方法。 消除了捕获在闪速EEPROM的隧穿氧化物中的电荷，以在扩展编程和擦除周期之后保持编程的阈值电压和擦除的阈值电压的适当分离。 通过首先向EEPROM单元的源施加高正电压脉冲，擦除快闪EEPROM单元开始擦除快闪EEPROM单元的方法。 同时，对半导体衬底和控制栅极施加接地参考电位。 在同一时间，排水沟漂浮。 将源极和漏极浮置并将接地参考电位施加到半导体衬底，然后去除快闪EEPROM单元。 同时，向控制栅极施加相对较大的负电压脉冲。

公开(公告)号：US5726933A

公开(公告)日：1998-03-10

申请号：US857162

申请日：1997-05-15

Applicant: Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

Inventor： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh ,  Ming-Chou Ho

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/06

CPC classification number: G11C16/14 ,  G11C16/10

Abstract: The present invention provides method to erase and program flash EEPROMS devices using a clipped sine waveform (Vg). The clipped sine waveform reduces the tunneling oxide electric field between the floating gate and the source or drain region thereby reducing electron trapping. The method for the erase cycle comprises: applying a positive voltage to a source region; grounding a well region; floating the drain region; and simultaneously applying a negative clipped sine waveform voltage to a control gate during the erase cycle. The program cycle of the invention comprises: applying a voltage to a drain region; grounding a well region; floating a source region; and simultaneously applying a clipped sine waveform voltage to the control gate whereby the clipped sine waveforms reduce the electric field in a tunnel oxide layer which reduces the electron trapping.

Abstract translation: 本发明提供了使用限幅正弦波形（Vg）擦除和编程闪存EEPROMS设备的方法。 限幅正弦波形减少了浮动栅极和源极或漏极区域之间的隧道氧化物电场，从而减少了电子俘获。 擦除周期的方法包括：向源极区域施加正电压; 接地井区; 漂浮漏极区; 并且在擦除周期期间同时向控制栅极施加负的限幅正弦波形电压。 本发明的程序循环包括：向漏区施加电压; 接地井区; 浮动源区; 并且同时向限制栅极施加限幅正弦波形电压，由此限幅正弦波形减少隧道氧化物层中的电场，从而减少电子捕获。

公开(公告)号：US5561387A

公开(公告)日：1996-10-01

申请号：US507532

申请日：1995-07-26

Applicant: Jian-Hsing Lee

Inventor： Jian-Hsing Lee

IPC: G01R31/26 ,  G01R31/22

CPC classification number: G01R31/2621

Abstract: The thickness of the gate insulation layer in an FET has been measured by relating it to its Fowler-Nordheim tunneling field. This Fowler-Nordheim tunneling field is measured in-situ and is non-destructive. Details of the method and apparatus are given.

Abstract translation: 已经通过将其与其Fowler-Nordheim隧道场相关联来测量FET中的栅极绝缘层的厚度。 这个Fowler-Nordheim隧道场是原位测量的，是非破坏性的。 给出方法和装置的细节。

公开(公告)号：US08018000B2

公开(公告)日：2011-09-13

申请号：US12046216

申请日：2008-03-11

Applicant: Shui-Hung Chen ,  Jian-Hsing Lee ,  Yung-Tien Tsai ,  Anthony Oates

Inventor： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yung-Tien Tsai ,  Anthony Oates

IPC: H01L23/62

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/42368

Abstract: Electrostatic discharge (ESD) protection in high voltage semiconductor devices is disclosed that provides enhanced current isolation between transistor drains or sources by creating an isolation island surrounding the drains or sources. This isolation island can be a higher-doped region within which the drain/source lies. The junction between the higher doping of this island region and the surrounding substrates operates to limit the amount of current that passes through the drain/source. Additionally, oxide features may be used to create an island surrounding the drain/source contact. Again, this isolating effect makes the amount of current passing through the device more uniform, which protects the device from damage due to an ESD event.

Abstract translation: 公开了高压半导体器件中的静电放电（ESD）保护，其通过产生围绕漏极或源极的隔离岛来提供晶体管漏极或源极之间的增强的电流隔离。 该隔离岛可以是漏极/源极所在的较高掺杂区域。 该岛区域和周围基板的较高掺杂之间的结点用于限制通过漏极/源极的电流量。 另外，可以使用氧化物特征来形成围绕漏极/源极接触的岛。 再次，这种隔离效应使得穿过器件的电流量更均匀，这保护了器件免受ESD事件的损害。

公开(公告)号：US07583484B2

公开(公告)日：2009-09-01

申请号：US10644718

申请日：2003-08-20

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC: H02H3/22

CPC classification number: H01L27/0285

Abstract: A sensor for electrostatic discharge (ESD) protection includes a voltage divider and a device coupled thereto. The sensor is coupled to an input terminal of the sensor, wherein a voltage drop occurs across the voltage divider and a high state voltage is generated at an output terminal of the sensor when an ESD voltage pulse is applied to the input terminal of the sensor. The device maintains the high state voltage at the output terminal of the sensor, while the ESD voltage pulse is applied to the input terminal of the sensor. A method for ESD protection includes the step of pulling down a gate terminal of a MOS transistor of an ESD circuit to a low state voltage when an ESD pulse is sensed.

Abstract translation: 用于静电放电（ESD）保护的传感器包括分压器和与其耦合的装置。 传感器耦合到传感器的输入端，其中在分压器上发生电压降，并且当ESD电压脉冲施加到传感器的输入端时，在传感器的输出端产生高的状态电压。 该装置在传感器的输出端保持高状态电压，同时将ESD电压脉冲施加到传感器的输入端。 ESD保护的方法包括当感测到ESD脉冲时将ESD电路的MOS晶体管的栅极端子下拉到低状态电压的步骤。

公开(公告)号：US20090179270A1

公开(公告)日：2009-07-16

申请号：US12046216

申请日：2008-03-11

Applicant: Shui-Hung Chen ,  Jian-Hsing Lee ,  Yung-Tien Tsai ,  Anthony Oates

Inventor： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yung-Tien Tsai ,  Anthony Oates

IPC: H01L23/62 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/42368

Abstract: Electrostatic discharge (ESD) protection in high voltage semiconductor devices is disclosed that provides enhanced current isolation between transistor drains or sources by creating an isolation island surrounding the drains or sources. This isolation island can be a higher-doped region within which the drain/source lies. The junction between the higher doping of this island region and the surrounding substrates operates to limit the amount of current that passes through the drain/source. Additionally, oxide features may be used to create an island surrounding the drain/source contact. Again, this isolating effect makes the amount of current passing through the device more uniform, which protects the device from damage due to an ESD event.

Abstract translation: 公开了高压半导体器件中的静电放电（ESD）保护，其通过产生围绕漏极或源极的隔离岛来提供晶体管漏极或源极之间的增强的电流隔离。 该隔离岛可以是漏极/源极所在的较高掺杂区域。 该岛区域和周围基板的较高掺杂之间的结点用于限制通过漏极/源极的电流量。 另外，可以使用氧化物特征来形成围绕漏极/源极接触的岛。 再次，这种隔离效应使得穿过器件的电流量更均匀，这保护了器件免受ESD事件的损害。

公开(公告)号：US07485905B2

公开(公告)日：2009-02-03

申请号：US11459650

申请日：2006-07-25

Applicant: Feng-Chi Hung ,  Jian-Hsing Lee ,  Hung-Lin Chen ,  Deng-Shun Chang

Inventor： Feng-Chi Hung ,  Jian-Hsing Lee ,  Hung-Lin Chen ,  Deng-Shun Chang

IPC: H01L29/80 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L29/0692 ,  H01L29/7835

Abstract: An electrostatic discharge protection device comprising a multi-finger gate, a first lightly doped region of a second conductivity, a first heavily doped region of the second conductivity, and a second lightly doped region of the second conductivity. The multi-finger gate comprises a plurality of fingers mutually connected in parallel over an active region of a first conductivity. The first lightly doped region of a second conductivity is disposed in the semiconductor substrate and between two of the fingers. The first heavily doped region of the second conductivity is disposed in the first lightly doped region of the second conductivity. The second lightly doped region of the second conductivity is beneath and adjoins the first lightly doped region of the second conductivity.

Abstract translation: 一种静电放电保护装置，包括多指门，具有第二导电性的第一轻掺杂区，第二导电性的第一重掺杂区和第二导电性的第二轻掺杂区。 多指门包括在第一导电性的有源区域上并联连接的多个指状物。 第二导电性的第一轻掺杂区域设置在半导体衬底中并且在两个指状物之间。 第二导电性的第一重掺杂区域设置在第二导电性的第一轻掺杂区域中。 第二导电性的第二轻掺杂区域位于第二导电性的第一轻掺杂区域的下方并与其邻接。

公开(公告)号：US20090008710A1

公开(公告)日：2009-01-08

申请号：US11773364

申请日：2007-07-03

Applicant: Chi-San Wei ,  Kuo-Ming Wu ,  Jian-Hsing Lee

Inventor： Chi-San Wei ,  Kuo-Ming Wu ,  Jian-Hsing Lee

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/0878

Abstract: A semiconductor device includes a gate electrode over a semiconductor substrate, wherein the gate electrode has a gate width direction; a source/drain region in the semiconductor substrate and adjacent the gate electrode, wherein the source/drain region has a first width in a direction parallel to the gate width direction; and a bulk pick-up region in the semiconductor substrate and abutting the source/drain region. The bulk pick-up region and the source/drain region have opposite conductivity types. The bulk pick-up region has a second width in the width direction, and wherein the second width is substantially less than the first width.

Abstract translation: 半导体器件包括在半导体衬底上的栅电极，其中栅电极具有栅极宽度方向; 在所述半导体衬底中并且与所述栅电极相邻的源极/漏极区域，其中所述源极/漏极区域在平行于所述栅极宽度方向的方向上具有第一宽度; 以及半导体衬底中的块体拾取区域并且邻接源极/漏极区域。 本体拾取区域和源极/漏极区域具有相反的导电类型。 本体拾取区域在宽度方向上具有第二宽度，并且其中第二宽度基本上小于第一宽度。

公开(公告)号：US07462885B2

公开(公告)日：2008-12-09

申请号：US11606424

申请日：2006-11-30

Applicant: Shui-Hung Chen ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  D. J. Perng ,  Anthony Oates

Inventor： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  D. J. Perng ,  Anthony Oates

IPC: H01L29/72 ,  H01L23/62

CPC classification number: H01L29/0847 ,  H01L27/0266 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: An electrostatic discharge-protected MOS structure is disclosed. An electrostatic discharge-protected MOS structure includes a semiconductor substrate of a first type, a first well of the first type formed in the semiconductor substrate, and a second well of a second type disposed adjacent to the first well. The MOS structure further includes a source region, a drain region, and an oxide layer and a polysilicon layer for forming a gate electrode of the MOS structure. In addition, the MOS structure includes a parasitic SCR comprising at least a parasitic NPN bipolar transistor and a buried layer of the second type interposed between the second well and the semiconductor substrate. The buried layer functions to lower a resistance of the semiconductor substrate during an ESD event so that ESD currents generated by the parasitic SCR are dissipated through the buried layer and the semiconductor substrate, thereby protecting the MOS structure.

Abstract translation: 公开了一种静电放电保护的MOS结构。 静电放电保护的MOS结构包括第一类型的半导体衬底，形成在半导体衬底中的第一类型的第一阱和与第一阱相邻布置的第二类型的第二阱。 MOS结构还包括用于形成MOS结构的栅电极的源极区，漏极区和氧化物层以及多晶硅层。 此外，MOS结构包括至少包括寄生NPN双极晶体管和插入在第二阱和半导体衬底之间的第二类型的掩埋层的寄生SCR。 掩埋层用于在ESD事件期间降低半导体衬底的电阻，使得由寄生SCR产生的ESD电流通过掩埋层和半导体衬底消散，从而保护MOS结构。

公开(公告)号：US07420252B2

公开(公告)日：2008-09-02

申请号：US11337147

申请日：2006-01-20

Applicant: Kuo-Ming Wu ,  Jian-Hsing Lee ,  Yi-Chun Lin ,  Chi-Chih Chen

Inventor： Kuo-Ming Wu ,  Jian-Hsing Lee ,  Yi-Chun Lin ,  Chi-Chih Chen

IPC: H01L23/62

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/4238

Abstract: A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; and a gate structure overlying parts of the first and second wells for controlling a current flowing between the first and second doped regions. A first spacing distance from an interface between the second doped region and the second well to its closest edge of the gate structure is greater than 200 percent of a second spacing distance from a center point of second doped region to the edge of the gate structure, thereby increasing impedance against an electrostatic discharge (ESD) current flowing between the first and second doped regions during an ESD event.

Abstract translation: 半导体器件包括设置在半导体衬底中的第一阱上的第一掺杂区; 第二掺杂区域，其设置在与所述半导体衬底中的所述第一阱相邻的第二阱上，所述第二掺杂区域的掺杂剂密度高于所述第二阱的掺杂剂密度; 以及覆盖第一和第二阱的部分的栅极结构，用于控制在第一和第二掺杂区域之间流动的电流。 从第二掺杂区域和第二阱之间的界面到其栅极结构的最近边缘的第一间隔距离大于从第二掺杂区域的中心点到栅极结构边缘的第二间隔距离的200％ 从而增加针对在ESD事件期间在第一和第二掺杂区域之间流动的静电放电（ESD）电流的阻抗。