公开(公告)号：US5913122A

公开(公告)日：1999-06-15

申请号：US789717

申请日：1997-01-27

申请人： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Jung-Ke Yeh ,  Hsiu-Han Liao

发明人： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Jung-Ke Yeh ,  Hsiu-Han Liao

IPC分类号： H01L21/336 ,  H01L27/092 ,  H01L29/08

CPC分类号： H01L29/66575 ,  H01L27/0928 ,  H01L29/0847

摘要： An FET semiconductor device comprises a doped silicon semiconductor substrate having surface. The substrate being doped with a first type of dopant. An N-well is formed within the surface of the P-substrate. A P-well is formed within the N-well forming a twin well. Field oxide regions are formed on the surface of the substrate located above borders between the wells and regions of the substrate surrounding the wells. A gate electrode structure is formed over the P-well between the field oxide regions. A source region and a drain region are formed in the surface of the substrate. The source region and the drain region are self-aligned with the gate electrode structure with the source region and the drain region being spaced away from the field oxide regions by a gap of greater than or equal to about 0.7 .mu.m.

摘要翻译： FET半导体器件包括具有表面的掺杂硅半导体衬底。 衬底被掺杂有第一类型的掺杂剂。 在P基板的表面内形成有N阱。 在形成双井的N阱内形成P阱。 位于位于井周围的边界之上的基板的表面上的场氧化物区域和围绕所述孔的基板的区域形成。 在场氧化物区域之间的P阱上形成栅电极结构。 源极区域和漏极区域形成在衬底的表面中。 源极区域和漏极区域与栅极电极结构自对准，源极区域和漏极区域与场氧化物区域间隔开大于或等于约0.7μm的间隙。

公开(公告)号：US5811856A

公开(公告)日：1998-09-22

申请号：US554994

申请日：1995-11-13

申请人： Jian-Hsing Lee

发明人： Jian-Hsing Lee

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0251 ,  H01L2924/0002

摘要： An object of this invention is the creation of an input protection circuit for highly dense integrated circuits that has improved ESD immunity. This is accomplished by the addition of a P.sup.+ diffusion adjacent to the emitter of a field device to make the base resistance of each of the field devices approximately equal. When an ESD source is contacted to the input protection circuit, the field devices will conduct simultaneously and with equal currents, thus preventing high current densities that can cause circuit failure.

摘要翻译： 本发明的目的是为具有改进的ESD抗扰度的高密度集成电路的创建输入保护电路。 这是通过在现场设备的发射极附近添加P +扩散来实现的，以使每个现场设备的基极电阻近似相等。 当ESD源与输入保护电路接触时，现场设备将以同等电流同时传导，从而防止可能导致电路故障的高电流密度。

公开(公告)号：US5659245A

公开(公告)日：1997-08-19

申请号：US658524

申请日：1996-06-03

申请人： King-Ho Ping ,  Jian-Hsing Lee

发明人： King-Ho Ping ,  Jian-Hsing Lee

IPC分类号： G01R1/18 ,  G01R31/28 ,  H05K1/02 ,  H05K3/00 ,  H05K9/00 ,  G01R31/02

CPC分类号： G01R31/2863 ,  G01R1/18 ,  H05K1/0218 ,  H05K1/0259 ,  H05K9/0067 ,  H05K1/0215 ,  H05K2201/09354 ,  H05K2201/10189 ,  H05K2201/10689 ,  H05K3/0061

摘要： A burn-in board assembly for the protection of integrated circuit modules from Electrostatic discharge and the shielding of said integrated circuit modules from Electromagnetic Interference during said electrostatic discharge is described. The burn-in board assembly has a printed circuit board onto which the integrated circuits are mounted by soldering or plugging into sockets soldered to said burnin board assembly. Disposed upon the printed circuit board is a plurality of input stimuli, feedback sensing, and output response signal traces to connect the integrated circuit modules to a connector that is coupled to a input stimulus generator and feedback sensing and output response monitor. Also disposed upon the printed circuit board is a plurality of ground traces and voltage supply traces to connect the integrated circuit modules to the connector that is coupled to a voltage supply source and the system ground reference point. An electrostatic discharge bypass track is disposed peripherally upon the printed circuit board and is connected to the ground reference point through the connector to prevent damage to the printed circuit modules during an electrostatic discharge event. A first and a second electromagnetic interference shielding trace is disposed upon the printed circuit board. Each electromagnetic shielding trace is connected at opposite ends to the ground reference point through the connector to shield the printed circuit traces from the effects of the electromagnetic interference.

摘要翻译： 描述了一种用于在静电放电期间保护集成电路模块免受静电放电和屏蔽所述集成电路模块与电磁干扰的老化板组件。 老化板组件具有印刷电路板，集成电路通过焊接或插入到焊接到所述燃烧板组件的插座中而安装在该印刷电路板上。 布置在印刷电路板上的是多个输入刺激，反馈感测和输出响应信号迹线，以将集成电路模块连接到耦合到输入激励发生器和反馈感测和输出响应监视器的连接器。 还布置在印刷电路板上的是多个接地迹线和电压提供迹线，用于将集成电路模块连接到耦合到电压源和系统接地参考点的连接器。 静电放电旁路轨道周边布置在印刷电路板上，并通过连接器连接到接地参考点，以防止在静电放电事件期间损坏印刷电路模块。 第一和第二电磁干扰屏蔽迹线设置在印刷电路板上。 每个电磁屏蔽迹线通过连接器在相对端连接到接地参考点，以屏蔽印刷电路迹线免受电磁干扰的影响。

公开(公告)号：US09362384B2

公开(公告)日：2016-06-07

申请号：US14559542

申请日：2014-12-03

申请人： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L29/66681 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

公开(公告)号：US07518843B2

公开(公告)日：2009-04-14

申请号：US11134539

申请日：2005-05-19

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC分类号： H02H9/00 ,  H02H3/22

CPC分类号： H01L27/0262

摘要： An ESD protection circuit includes a silicon controlled rectifier coupled between a circuit pad and ground for bypassing an ESD current from the circuit pad during an ESD event. An MOS transistor, having a source shared with the silicon controlled rectifier, is coupled between the pad and ground for reducing a trigger voltage of the silicon controlled rectifier during the ESD event. The silicon controlled rectifier has a first diode serially connected to a second diode in an opposite direction, between the pad and the shared source of the MOS transistor, for functioning as a bipolar transistor. In a layout view, a first area for placement of the first and second diodes is interposed between at least two separate sets of second areas for placement of the MOS transistor.

摘要翻译： ESD保护电路包括耦合在电路焊盘和地之间的可控硅整流器，用于在ESD事件期间旁路来自电路板的ESD电流。 具有与可控硅整流器共享的源极的MOS晶体管耦合在焊盘和地之间，以在ESD事件期间降低可控硅整流器的触发电压。 可控硅整流器具有在与MOS晶体管的焊盘和共享源之间的相反方向上串联连接到第二二极管的第一二极管，用作双极晶体管。 在布局图中，用于放置第一和第二二极管的第一区域介于至少两个分开的第二区域组之间，用于放置MOS晶体管。

公开(公告)号：US07518192B2

公开(公告)日：2009-04-14

申请号：US10985532

申请日：2004-11-10

申请人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Chin Yang

发明人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Chin Yang

IPC分类号： H01L23/62

CPC分类号： H01L21/76816 ,  H01L27/0274 ,  H01L29/78

摘要： A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the source and drain side. A plurality of first level vias is electrically coupled to the GGNMOS and has a substantially asymmetrical layout in the source and drain regions. A second level via(s) re-routes the ESD current to the desired first level vias. The uniformity of the current flow in the GGNMOS is improved.

摘要翻译： 提出了一种用于静电放电保护的半导体结构。 半导体结构包括具有衬底，栅极电极，源极区域和漏极区域的接地栅极nMOS（GGNMOS）。 在源极和漏极侧形成多个接触插塞。 多个第一级通孔电耦合到GGNMOS并且在源极和漏极区域中具有基本不对称的布局。 第二级通过将ESD电流重新路由到期望的第一级通孔。 GGNMOS中电流的均匀性得到改善。

公开(公告)号：US07508639B2

公开(公告)日：2009-03-24

申请号：US11305983

申请日：2005-12-19

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H02H9/00 ,  H02H3/22 ,  H02H1/00 ,  H02H1/04 ,  H02H9/06 ,  H01C7/12

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Input/output devices with robustness of ESD protection are provided. An input/output device comprises an input/output pad, a first NMOS transistor, a second NMOS transistor and an ESD detector. The first NMOS transistor comprises a first drain, a first source and a first gate, wherein the first source and the first gate are coupled to a first ground power rail, and the first drain to the input/output pad. The second NMOS transistor comprises a second drain, a second source and a second gate, wherein the second source is coupled to the first ground power rail, the second drain to the input/output pad, and the second gate to a first pre-driver. When an ESD event is detected, the ESD detector makes the first pre-driver couple the second gate to the first ground power rail, thereby the first and second transistors evenly discharge ESD current.

摘要翻译： 提供具有ESD保护鲁棒性的输入/输出设备。 输入/输出装置包括输入/​​输出焊盘，第一NMOS晶体管，第二NMOS晶体管和ESD检测器。 第一NMOS晶体管包括第一漏极，第一源极和第一栅极，其中第一源极和第一栅极耦合到第一接地电源轨，第一漏极耦合到输入/输出焊盘。 第二NMOS晶体管包括第二漏极，第二源极和第二栅极，其中第二源极耦合到第一接地电源轨，第二漏极耦合到输入/输出焊盘，第二栅极耦合到第一预驱动器 。 当检测到ESD事件时，ESD检测器使第一预驱动器将第二栅极耦合到第一接地电源轨，由此第一和第二晶体管均匀地放电ESD电流。

公开(公告)号：US07485930B2

公开(公告)日：2009-02-03

申请号：US11622574

申请日：2007-01-12

申请人： Jian-Hsing Lee ,  Shui-Hunyi Chen

发明人： Jian-Hsing Lee ,  Shui-Hunyi Chen

IPC分类号： H01L23/62

CPC分类号： H01L27/0255

摘要： The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

摘要翻译： 本发明描述了一种用于提供具有降低的输入电容的ESD半导体保护的结构和工艺。 该结构由围绕I / O ESD保护器件和Vcc至Bss保护器件的重掺杂P +保护环组成。 另外，在I / O保护器件的P +保护环周围还有一个重掺杂的N +保护环。 保护环增强结构二极管元件，提供增强的ESD能量放电路径能力，从而能够消除特定的常规Vss至I / O焊盘ESD保护器件。 这降低了I / O电路所看到的电容，同时为有源电路器件提供足够的ESD保护。

公开(公告)号：US07465994B2

公开(公告)日：2008-12-16

申请号：US11512850

申请日：2006-08-29

申请人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

发明人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at one side of the first conductive gate layer. The third doped region has a polarity different from that of the first and second doped regions, such that the third doped region and the second doped region form a diode for enhancing dissipation of ESD current during a negative ESD event.

摘要翻译： ESD保护电路的布局结构包括：第一MOS器件区域，具有设置在第一导电栅极层的两侧的具有相同极性的第一和第二掺杂区域;以及第三掺杂区域，沿第一掺杂区域设置在一侧 的第一导电栅极层。 第三掺杂区域具有与第一和第二掺杂区域不同的极性，使得第三掺杂区域和第二掺杂区域形成用于在负ESD事件期间增强ESD电流的耗散的二极管。

公开(公告)号：US20080211027A1

公开(公告)日：2008-09-04

申请号：US11713193

申请日：2007-03-01

申请人： Shu Huei Lin ,  Jian-Hsing Lee ,  Shao-Chang Huang ,  Cheng Hsu Wu ,  Chuan Ying Lee

发明人： Shu Huei Lin ,  Jian-Hsing Lee ,  Shao-Chang Huang ,  Cheng Hsu Wu ,  Chuan Ying Lee

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad, at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND, at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region, and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND, wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell than the NMOS transistor.

摘要翻译： 一种连接到集成电路中的接合焊盘的静电放电（ESD）结构，包括：具有连接到低电压源（GND）的一个或多个第一P +区的P型衬底，形成在P型衬底中的第一Nwell 设置在所述第一Nwell内并连接到所述接合焊盘的一个或多个第二P +区域，设置在所述第一N阱之外但在所述P型衬底中并连接到所述GND的至少一个第一N +区域，设置至少一个第二N +区域 在第一N阱之外，但在P型衬底中并连接到焊盘，其中第二N +区域比第一N +区域远离第一Nwell区域，并且至少一个导电材料设置在P型衬底之上 第一N +区和第二N +区，并且耦合到GND，其中第一N +区，第二N +区和导电材料分别形成NMOS晶体管的源极，漏极和栅极，并且第一P +区域更远 从第一个Nwell比NMOS晶体管。