Compacting test responses using X-driven compactor
    61.
    发明授权
    Compacting test responses using X-driven compactor 有权
    使用X驱动压实机压实测试响应

    公开(公告)号:US07779322B1

    公开(公告)日:2010-08-17

    申请号:US11898070

    申请日:2007-09-07

    IPC分类号: G01R31/28

    CPC分类号: G01R31/318547

    摘要: A method and apparatus for compacting test responses containing unknown values in a scan-based integrated circuit. The proposed X-driven compactor comprises a chain-switching matrix block and a space compaction logic block. The chain-switching matrix block switches the internal scan chain outputs before feeding them to the space compaction logic block for compaction so as to minimize X-induced masking and error masking. The X-driven compactor further selectively includes a finite-memory compaction logic block to further compact the outputs of the space compaction logic block.

    摘要翻译: 一种在基于扫描的集成电路中压缩包含未知值的测试响应的方法和装置。 所提出的X驱动压实机包括链切换矩阵块和空间压缩逻辑块。 链路切换矩阵块在将它们馈送到空间压缩逻辑块以进行压缩之前切换内部扫描链输出,以最小化X诱导的掩蔽和错误掩蔽。 X驱动压实机还选择性地包括有限存储器压缩逻辑块,以进一步压缩空间压缩逻辑块的输出。

    Wall Bushing For Air Conditioner
    63.
    发明申请
    Wall Bushing For Air Conditioner 失效
    空调墙壁衬套

    公开(公告)号:US20080211227A1

    公开(公告)日:2008-09-04

    申请号:US11911790

    申请日:2006-04-13

    IPC分类号: F16L5/00

    摘要: A wall-penetrating sleeve of air conditioner comprises external pipe and internal pipe. The cross section of the external pipe is “sports ground” shape, and an inner circular wall of the external pipe is tangential to an outer circular wall of the internal pipe. An end of the internal pipe is connected to an air outlet port of the air conditioner, and an end of the external pipe is connected to an air inlet port. This invention prevents an air outlet pipe of a mobile air conditioner from sliding off the wall body.

    摘要翻译: 空调墙壁穿透套管包括外管和内管。 外管的横截面是“运动场”形状,外管的内圆壁与内管的外圆壁相切。 内管的一端连接到空调的出风口,外管的一端与进气口连接。 本发明防止移动空调的出气管从墙体滑出。

    Flash memory with high-K dielectric material between substrate and gate
    64.
    发明授权
    Flash memory with high-K dielectric material between substrate and gate 有权
    闪存与衬底和栅极之间的高K电介质材料

    公开(公告)号:US07414281B1

    公开(公告)日:2008-08-19

    申请号:US10658936

    申请日:2003-09-09

    IPC分类号: H01L29/76

    CPC分类号: H01L29/513 H01L29/7881

    摘要: A flash memory cell and a method of forming the same are described. The flash memory cell may include a substrate having a source and a drain, a gate element, and a dielectric layer between the substrate and the gate element. The dielectric layer includes a dielectric material having a dielectric constant that is greater than that of silicon dioxide.

    摘要翻译: 描述闪存单元及其形成方法。 闪速存储单元可以包括在衬底和栅极元件之间具有源极和漏极的衬底,栅极元件和介电层。 电介质层包括介电常数大于二氧化硅的电介质材料。

    Memory cell with reduced DIBL and Vss resistance
    66.
    发明申请
    Memory cell with reduced DIBL and Vss resistance 有权
    具有降低的DIBL和Vss电阻的存储单元

    公开(公告)号:US20060035431A1

    公开(公告)日:2006-02-16

    申请号:US10915771

    申请日:2004-08-11

    IPC分类号: H01L21/336

    CPC分类号: H01L29/66825

    摘要: According to one exemplary embodiment, a method for fabricating a floating gate memory cell on substrate comprises a step of forming a spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in substrate. The method further comprises forming a high energy implant doped region adjacent to the spacer in the source region of substrate. The method further comprises forming a recess in a source region of the substrate, where the recess has a sidewall, a bottom, and a depth, and where the sidewall of the recess is situated adjacent to a source of the floating gate memory cell. According to this exemplary embodiment, the spacer causes the source to have a reduced lateral straggle and diffusion in the channel region, which causes a reduction in drain induced barrier lowering (DIBL) in the floating gate memory cell.

    摘要翻译: 根据一个示例性实施例,用于在衬底上制造浮动栅极存储器单元的方法包括形成与层叠栅极结构的源极侧壁相邻的间隔物的步骤,其中堆叠的栅极结构位于衬底中的沟道区域之上。 该方法还包括在衬底的源区中形成与间隔物相邻的高能注入掺杂区。 该方法还包括在衬底的源极区域中形成凹部,其中凹部具有侧壁,底部和深度,并且凹部的侧壁位于与浮动栅极存储单元的源极相邻的位置。 根据该示例性实施例,间隔件导致源极在通道区域中具有减小的横向偏移和扩散,这导致浮动栅极存储单元中的漏极感应势垒降低(DIBL)的减小。

    Hearing aid
    67.
    发明申请
    Hearing aid 有权
    助听器

    公开(公告)号:US20050163333A1

    公开(公告)日:2005-07-28

    申请号:US10502367

    申请日:2003-01-24

    IPC分类号: A61F11/00 H04R25/00

    摘要: The present invention relates to a hearing aid system comprising a hearing implant and a method of powering a hearing implant, the system comprising an external ear canal module and an implant, wherein the signalling and/or powering of the ear implant is by way of a light signal being provided to the implant through the ear drum from, for example, the ear canal module.

    摘要翻译: 本发明涉及一种助听器系统,其包括听力植入物和为听力植入物提供动力的方法,所述系统包括外耳道模块和植入物,其中所述耳朵植入物的信号和/或动力通过 光信号通过耳鼓从例如耳道模块提供给植入物。

    Method to distinguish an STI outer edge current component with an STI normal current component
    68.
    发明授权
    Method to distinguish an STI outer edge current component with an STI normal current component 失效
    区分STI外缘电流分量与STI正常电流分量的方法

    公开(公告)号:US06576487B1

    公开(公告)日:2003-06-10

    申请号:US10126363

    申请日:2002-04-19

    IPC分类号: G01R3126

    摘要: The present invention details a method which characterizes an STI fabrication process, and more particularly provides information relating to a variation in the STI sidewall profile between trenches in a middle portion of an array and a trench on an outer portion thereof. The method comprises forming two STI arrays with an STI fabrication process, forming a conductive layer over each array, biasing each conductive layer and determining a current associated therewith. The two current are then utilized to ascertain the variation of interest.

    摘要翻译: 本发明详细描述了一种表征STI制造工艺的方法,并且更具体地提供了与阵列的中间部分中的沟槽和其外部部分上的沟槽之间的STI侧壁轮廓变化有关的信息。 该方法包括用STI制造工艺形成两个STI阵列,在每个阵列上形成导电层,偏置每个导电层并确定与之相关联的电流。 然后利用两个电流来确定兴趣的变化。

    Low defect density process for deep sub-0.18 &mgr;m flash memory technologies
    69.
    发明授权
    Low defect density process for deep sub-0.18 &mgr;m flash memory technologies 失效
    用于深亚0.18微米闪存技术的低缺陷密度工艺

    公开(公告)号:US06541338B2

    公开(公告)日:2003-04-01

    申请号:US09917182

    申请日:2001-07-30

    IPC分类号: H01L218247

    CPC分类号: H01L27/115 H01L27/11521

    摘要: A method of forming flash memory EEPROM devices having a low energy source implant and a high-energy VSS connection implant such that the intrinsic source defect density is reduced and the VSs resistance is low. The source regions are implanted with a low energy, low dosage dopant ions and the VSS regions are implanted with a high energy, high dosage dopant ions.

    摘要翻译: 一种形成具有低能量源注入和高能量VSS连接注入的闪存EEPROM器件的方法,使得本征源缺陷密度降低并且VSs电阻低。 源区域注入低能量,低剂量掺杂剂离子,VSS区域注入高能量,高剂量掺杂剂离子。