公开(公告)号：US06524908B2

公开(公告)日：2003-02-25

申请号：US09872603

申请日：2001-06-01

申请人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Hsu ,  Keith Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Hsu ,  Keith Kwong Hon Wong

IPC分类号： H01L218242

CPC分类号： H01L28/75 ,  C23C14/0073 ,  C23C14/0641 ,  H01L21/2855 ,  H01L21/28568

摘要： A method forforming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N2 gas is then flown into the sputtering chamber until that the concentration of N2 gas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The N2 gas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.

摘要翻译： 描述了一种在半导体结构中形成难熔金属 - 硅 - 氮电容器的方法和形成的结构。 在该方法中，首先将预处理的半导体衬底定位在溅射室中。 然后将Ar气体流入溅射室，以从耐火金属硅化物靶或从难熔金属和硅的两个靶溅射沉积在衬底上的第一难熔金属 - 硅 - 氮层。 然后将N 2气体流入溅射室，直到室内的N 2气体的浓度至少为35％，以在第一难熔金属 - 硅 - 氮层的顶部溅射沉积第二难熔金属 - 硅 - 氮层。 然后停止N 2气流以在第二难熔金属 - 硅 - 氮层的顶部溅射沉积第三难熔金属 - 硅 - 氮层。 然后将难熔金属硅 - 氮的多层堆叠光刻形成电容器。

公开(公告)号：US20050227480A1

公开(公告)日：2005-10-13

申请号：US10817179

申请日：2004-04-02

申请人： Lawrence Clevenger ,  Louis Hsu ,  Christy Tyberg ,  Tsorng-Dih Yuan

发明人： Lawrence Clevenger ,  Louis Hsu ,  Christy Tyberg ,  Tsorng-Dih Yuan

IPC分类号： H01L21/31 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/5222 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for fabricating a low dielectric constant semiconductor comprising the steps of: depositing a first metal layer on a substrate; patterning the first metal layer to produce a patterned first metal wiring; applying a first insulating material onto the patterned first metal wiring to form a support structure; patterning the first insulating material by a contact printing process; depositing a second insulating material of lower dielectric constant onto the support structure; planarizing the second insulating material; depositing a polish-stop film layer over the planarized second insulating material, thereby forming a plurality of metal studs; depositing a second metal layer onto the polish-stop film layer forming interconnects with said studs; and patterning the metal layer to produce a second metal wiring interconnecting to the first wiring via the metal studs.

摘要翻译： 一种制造低介电常数半导体的方法，包括以下步骤：在衬底上沉积第一金属层; 图案化第一金属层以产生图案化的第一金属布线; 将第一绝缘材料施加到所述图案化的第一金属布线上以形成支撑结构; 通过接触印刷方法图案化第一绝缘材料; 将较低介电常数的第二绝缘材料沉积到所述支撑结构上; 平面化第二绝缘材料; 在平坦化的第二绝缘材料上沉积抛光停止膜层，从而形成多个金属螺柱; 将第二金属层沉积到所述抛光 - 停止膜层上，形成与所述螺柱的互连; 以及图案化所述金属层以产生经由所述金属螺柱与所述第一布线互连的第二金属布线。

公开(公告)号：US06624526B2

公开(公告)日：2003-09-23

申请号：US09872325

申请日：2001-06-01

申请人： Lawrence Clevenger ,  Louis Hsu ,  Li-Kong Wang

发明人： Lawrence Clevenger ,  Louis Hsu ,  Li-Kong Wang

IPC分类号： H01L2711

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

摘要： A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.

摘要翻译： 描述了一种紧凑的SRAM单元，其包含难熔金属硅 - 氮电阻元件作为其上拉晶体管，其包括半导体衬底，一对NMOS传输器件，其通过金属导体在蚀刻衬底的侧壁上垂直形成，提供 衬底中n +区和顶部位线之间的电气通信，连接到接地互连的衬底上的一对下拉nMOS器件以及由难熔金属硅形成的一对垂直高电阻元件 - 并且作为连接到Vdd的负载。 本发明还描述了一种用于制造这种紧凑的SRAM单元的方法。

公开(公告)号：US20070007601A1

公开(公告)日：2007-01-11

申请号：US11509866

申请日：2006-08-25

申请人： Louis Hsu ,  Oleg Gluschenkov ,  Jack Mandelman ,  Carl Radens

发明人： Louis Hsu ,  Oleg Gluschenkov ,  Jack Mandelman ,  Carl Radens

IPC分类号： H01L21/8244 ,  H01L29/94 ,  H01L29/76

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

摘要： A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.

摘要翻译： 形成SRAM单元装置的方法包括以下步骤。 形成栅极FET晶体管并形成一对垂直下拉FET晶体管，其具有第一共同体和第一公共源，图案化为形成在平面绝缘体上的平行岛的硅层。 通过交叉耦合的反相器FET晶体管之间的上扩散来蚀刻，以形成将一对垂直下拉FET晶体管的上拉和下拉漏极区的上层平分的下拉隔离空间，隔离空间达到 到共同的身体层。 形成一对具有第二共同体和第二公共漏极的垂直上拉FET晶体管。 然后，连接FET晶体管以形成SRAM单元。

公开(公告)号：US20050087814A1

公开(公告)日：2005-04-28

申请号：US10995444

申请日：2004-11-23

申请人： Louis Hsu ,  Jack Mandelman ,  Carl Radens ,  Richard Strub ,  William Tonti

发明人： Louis Hsu ,  Jack Mandelman ,  Carl Radens ,  Richard Strub ,  William Tonti

IPC分类号： H01L21/8239 ,  H01L21/334 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/94 ,  H01L21/8238

CPC分类号： H01L29/66181 ,  H01L21/823462 ,  H01L27/10861 ,  H01L27/10894 ,  H01L29/945

摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.

公开(公告)号：US07329600B2

公开(公告)日：2008-02-12

申请号：US10817179

申请日：2004-04-02

申请人： Lawrence Clevenger ,  Louis Hsu ,  Christy S. Tyberg ,  Tsorng-Dih Yuan

发明人： Lawrence Clevenger ,  Louis Hsu ,  Christy S. Tyberg ,  Tsorng-Dih Yuan

IPC分类号： H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for fabricating a low dielectric constant semiconductor comprising the steps of: depositing a first metal layer on a substrate; patterning the first metal layer to produce a patterned first metal wiring; applying a first insulating material onto the patterned first metal wiring to form a support structure; patterning the first insulating material by a contact printing process; depositing a second insulating material of lower dielectric constant onto the support structure; planarizing the second insulating material; depositing a polish-stop film layer over the planarized second insulating material, thereby forming a plurality of metal studs; depositing a second metal layer onto the polish-stop film layer forming interconnects with said studs; and patterning the metal layer to produce a second metal wiring interconnecting to the first wiring via the metal studs.

摘要翻译： 一种制造低介电常数半导体的方法，包括以下步骤：在衬底上沉积第一金属层; 图案化第一金属层以产生图案化的第一金属布线; 将第一绝缘材料施加到所述图案化的第一金属布线上以形成支撑结构; 通过接触印刷方法图案化第一绝缘材料; 将较低介电常数的第二绝缘材料沉积到所述支撑结构上; 平面化第二绝缘材料; 在平坦化的第二绝缘材料上沉积抛光停止膜层，从而形成多个金属螺柱; 将第二金属层沉积到所述抛光 - 停止膜层上，形成与所述螺柱的互连; 以及图案化所述金属层以产生经由所述金属螺柱与所述第一布线互连的第二金属布线。

公开(公告)号：US06707097B2

公开(公告)日：2004-03-16

申请号：US10346437

申请日：2003-01-16

申请人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Hsu ,  Keith Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Hsu ,  Keith Kwong Hon Wong

IPC分类号： H01L218242

CPC分类号： H01L28/75 ,  C23C14/0073 ,  C23C14/0641 ,  H01L21/2855 ,  H01L21/28568

摘要： A method for forming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N2 gas is then flown into the sputtering chamber until that the concentration of N2 gas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The N2 gas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.

摘要翻译： 描述了在半导体结构中形成难熔金属 - 硅 - 氮电容器的方法和形成的结构。 在该方法中，首先将预处理的半导体衬底定位在溅射室中。 然后将Ar气体流入溅射室，以从耐火金属硅化物靶或从难熔金属和硅的两个靶溅射沉积在衬底上的第一难熔金属 - 硅 - 氮层。 然后将N 2气体流入溅射室，直到室内的N 2气体的浓度至少为35％，以在第一难熔金属 - 硅 - 氮层的顶部溅射沉积第二难熔金属 - 硅 - 氮层。 然后停止N 2气流以在第二难熔金属 - 硅 - 氮层的顶部溅射沉积第三难熔金属 - 硅 - 氮层。 然后将难熔金属硅 - 氮的多层堆叠光刻形成电容器。

公开(公告)号：US20070235833A1

公开(公告)日：2007-10-11

申请号：US11393142

申请日：2006-03-30

申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

IPC分类号： H01L29/00

CPC分类号： H01L27/10841 ,  H01L27/10864

摘要： Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material separates the first and second doped regions. A third doped region is defined in the semiconductor material bordering the sidewall of the trench and disposed between the first and second doped regions. The third doped region is doped to have a second conductivity type opposite to the first conductivity type. Methods for forming the doped regions involve depositing either a layer of a material doped with both dopants or different layers each doped with one of the dopants in the trench and, then, diffusing the dopants from the layer or layers into the semiconductor material bordering the trench sidewall.

摘要翻译： 具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法。 半导体结构包括限定在与沟槽的侧壁相邻的衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。 半导体材料的中间区域分离第一和第二掺杂区域。 第三掺杂区域限定在与沟槽的侧壁接壤并且设置在第一和第二掺杂区域之间的半导体材料中。 第三掺杂区被掺杂以具有与第一导电类型相反的第二导电类型。 用于形成掺杂区域的方法包括沉积掺杂有掺杂剂或不同层的材料的层，每个掺杂剂或不同的层在沟槽中掺杂有一种掺杂剂，然后将掺杂剂从层或层扩散到与沟槽接壤的半导体材料 侧壁。

公开(公告)号：US20070035342A1

公开(公告)日：2007-02-15

申请号：US11203860

申请日：2005-08-15

申请人： Minhan Chen ,  Westerfield Ficken ,  Louis Hsu ,  Steven Zier

发明人： Minhan Chen ,  Westerfield Ficken ,  Louis Hsu ,  Steven Zier

IPC分类号： H03F3/45

CPC分类号： H03F3/45197 ,  H03F2203/45424 ,  H03F2203/45431 ,  H03F2203/45488 ,  H03F2203/45646

摘要： Offset voltages in differential amplifiers are minimized by controlling compensation currents through the load impedances of the amplifiers. The currents are varied while sensing the polarity of the offset voltage. When the polarity changes, the current values are latched to keep the offset voltage at a minimum.

公开(公告)号：US20060284251A1

公开(公告)日：2006-12-21

申请号：US11155030

申请日：2005-06-16

申请人： Louis Hsu ,  Jack Mandelman

发明人： Louis Hsu ,  Jack Mandelman

IPC分类号： H01L27/12

CPC分类号： H01L29/045 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207

摘要： In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.