公开(公告)号：US06524908B2

公开(公告)日：2003-02-25

申请号：US09872603

申请日：2001-06-01

申请人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Hsu ,  Keith Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Hsu ,  Keith Kwong Hon Wong

IPC分类号： H01L218242

CPC分类号： H01L28/75 ,  C23C14/0073 ,  C23C14/0641 ,  H01L21/2855 ,  H01L21/28568

摘要： A method forforming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N2 gas is then flown into the sputtering chamber until that the concentration of N2 gas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The N2 gas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.

摘要翻译： 描述了一种在半导体结构中形成难熔金属 - 硅 - 氮电容器的方法和形成的结构。 在该方法中，首先将预处理的半导体衬底定位在溅射室中。 然后将Ar气体流入溅射室，以从耐火金属硅化物靶或从难熔金属和硅的两个靶溅射沉积在衬底上的第一难熔金属 - 硅 - 氮层。 然后将N 2气体流入溅射室，直到室内的N 2气体的浓度至少为35％，以在第一难熔金属 - 硅 - 氮层的顶部溅射沉积第二难熔金属 - 硅 - 氮层。 然后停止N 2气流以在第二难熔金属 - 硅 - 氮层的顶部溅射沉积第三难熔金属 - 硅 - 氮层。 然后将难熔金属硅 - 氮的多层堆叠光刻形成电容器。

公开(公告)号：US06707097B2

公开(公告)日：2004-03-16

申请号：US10346437

申请日：2003-01-16

申请人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Hsu ,  Keith Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Hsu ,  Keith Kwong Hon Wong

IPC分类号： H01L218242

CPC分类号： H01L28/75 ,  C23C14/0073 ,  C23C14/0641 ,  H01L21/2855 ,  H01L21/28568

摘要： A method for forming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N2 gas is then flown into the sputtering chamber until that the concentration of N2 gas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The N2 gas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.

摘要翻译： 描述了在半导体结构中形成难熔金属 - 硅 - 氮电容器的方法和形成的结构。 在该方法中，首先将预处理的半导体衬底定位在溅射室中。 然后将Ar气体流入溅射室，以从耐火金属硅化物靶或从难熔金属和硅的两个靶溅射沉积在衬底上的第一难熔金属 - 硅 - 氮层。 然后将N 2气体流入溅射室，直到室内的N 2气体的浓度至少为35％，以在第一难熔金属 - 硅 - 氮层的顶部溅射沉积第二难熔金属 - 硅 - 氮层。 然后停止N 2气流以在第二难熔金属 - 硅 - 氮层的顶部溅射沉积第三难熔金属 - 硅 - 氮层。 然后将难熔金属硅 - 氮的多层堆叠光刻形成电容器。

公开(公告)号：US06700203B1

公开(公告)日：2004-03-02

申请号：US09686742

申请日：2000-10-11

申请人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

IPC分类号： H01L2348

CPC分类号： H01L28/20 ,  H01L27/0688

摘要： An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.

摘要翻译： 公开了一种具有原位形成的单位电阻器的电子结构及其制造方法。 具有原位形成的单元电阻器的电子结构由形成在绝缘材料层中的第一多个导电元件组成，多个电阻通孔形成在顶部并与第一多个导电元件中的至少一个电连通 以及形成在所述多个电阻通孔中的至少一个上方并与之电气连通的第二多个导电元件。 本发明的新颖结构可以进一步形成为多电平配置，使得多电平电阻器可以串联连接以提供更大的电阻值。 本发明的新颖结构还可以与电容器网络组合以形成期望的RC电路。

公开(公告)号：US06794226B2

公开(公告)日：2004-09-21

申请号：US10374395

申请日：2003-02-26

申请人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

IPC分类号： H01L2182

CPC分类号： H01L21/76849 ,  H01L21/7687 ,  H01L21/76888 ,  H01L23/5258 ,  H01L27/0629 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.

摘要翻译： 公开了一种半导体结构，其包括由难熔金属 - 硅 - 氮形成的熔丝，扩散阻挡层或电容器的至少一个电路元件。 还公开了一种通过难熔金属硅 - 氮材料制造这种半导体结构的方法，其包括熔丝元件，扩散阻挡层，电阻器或电容器。 要使用的合适的难熔金属 - 硅 - 氮材料是TaSiN，其通过改变Ta:Si:N的比例来提供宽范围的电阻率。 本发明提供了通过TaSiN层的单个沉积工艺可以形成扩散阻挡层，保险丝，电容器和电阻器的各种组件的优点，然后通过热处理或离子注入对各种组分进行选择性掩蔽和处理， 选择性地改变其电阻率，同时保持其他屏蔽元件具有相同的电阻率。

公开(公告)号：US06831369B2

公开(公告)日：2004-12-14

申请号：US10705115

申请日：2003-11-10

申请人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

IPC分类号： H01L2348

CPC分类号： H01L28/20 ,  H01L27/0688

摘要： An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.

摘要翻译： 公开了一种具有原位形成的单位电阻器的电子结构及其制造方法。 具有原位形成的单元电阻器的电子结构由形成在绝缘材料层中的第一多个导电元件组成，多个电阻通孔形成在顶部并与第一多个导电元件中的至少一个电连通 以及形成在所述多个电阻通孔中的至少一个上方并与之电气连通的第二多个导电元件。 本发明的新颖结构可以进一步形成为多电平配置，使得多电平电阻器可以串联连接以提供更大的电阻值。 本发明的新颖结构还可以与电容器网络组合以形成期望的RC电路。

公开(公告)号：US06545339B2

公开(公告)日：2003-04-08

申请号：US09760245

申请日：2001-01-12

申请人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

IPC分类号： H01L27108

CPC分类号： H01L21/76849 ,  H01L21/7687 ,  H01L21/76888 ,  H01L23/5258 ,  H01L27/0629 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.

公开(公告)号：US06828232B2

公开(公告)日：2004-12-07

申请号：US10705116

申请日：2003-11-10

申请人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

发明人： Cyril Cabral, Jr. ,  Lawrence Clevenger ,  Louis Lu-Chen Hsu ,  Keith Kwong Hon Wong

IPC分类号： H01L214763

CPC分类号： H01L28/20 ,  H01L27/0688

摘要： An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.

公开(公告)号：US08362600B2

公开(公告)日：2013-01-29

申请号：US12689268

申请日：2010-01-19

申请人： Cyril Cabral, Jr. ,  Michael S. Gordon ,  David F. Heidel ,  Conal Eugene Murray ,  Kenneth Parker Rodbell ,  Henry Hong Ki Tang

发明人： Cyril Cabral, Jr. ,  Michael S. Gordon ,  David F. Heidel ,  Conal Eugene Murray ,  Kenneth Parker Rodbell ,  Henry Hong Ki Tang

IPC分类号： H01L23/556 ,  H01L21/60

CPC分类号： H01L23/556 ,  H01L24/13 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00

摘要： A method is disclosed that includes providing a semiconductor substrate having one or more device levels including a number of devices, and forming a number of wiring levels on a top surface of the one or more device levels, wherein one or more of the number of wiring levels includes one or more alpha particle blocking shields situated between at least one of the number of devices and a predetermined first location where a terminal pad will be formed in one of the wiring levels, the one or more alpha particle blocking shields placed at a second location, having one or more widths, and occupying a predetermined number of the wiring levels, sufficient to prevent a predetermined percentage of alpha particles of a selected energy or less expected to be emitted from an alpha particle emitting metallization to be formed adjacent and connected to the terminal pad from reaching the one device.

摘要翻译： 公开了一种方法，其包括提供具有包括多个器件的一个或多个器件电平的半导体衬底，以及在所述一个或多个器件级的顶表面上形成多个布线电平，其中所述多个布线中的一个或多个 水平包括一个或多个α粒子阻挡屏蔽，位于多个器件中的至少一个与预定的第一位置之间，其中端子焊盘将形成在一个布线层中，一个或多个α粒子阻挡屏蔽放置在第二个 位置，具有一个或多个宽度并且占据预定数量的布线水平，足以防止预定百分比的α粒子被选择的能量或预期从发射的α粒子发射的金属化物发射出来邻近并连接到 终端垫到达一个设备。

公开(公告)号：US08193051B2

公开(公告)日：2012-06-05

申请号：US13047172

申请日：2011-03-14

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US08129267B2

公开(公告)日：2012-03-06

申请号：US12052881

申请日：2008-03-21

申请人： Cyril Cabral, Jr. ,  K. Paul Muller ,  Kenneth P. Rodbell

发明人： Cyril Cabral, Jr. ,  K. Paul Muller ,  Kenneth P. Rodbell

IPC分类号： H01L21/4763

CPC分类号： H01L23/5223 ,  H01L23/3192 ,  H01L23/53238 ,  H01L23/556 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/02166 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/10125 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13007 ,  H01L2224/13028 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13487 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/05552 ,  H01L2924/00

摘要： An alpha particle blocking structure and method of making the structure. The structure includes: a semiconductor substrate; a set of interlevel dielectric layers stacked from a lowermost interlevel dielectric layer closest to the substrate to a uppermost interlevel dielectric layer furthest from the substrate, each interlevel dielectric layer of the set of interlevel dielectric layers including electrically conductive wires, top surfaces of the wires substantially coplanar with top surfaces of corresponding interlevel dielectric layers; an electrically conductive tot final pad contacting a wire pad of the uppermost interlevel dielectric layer; an electrically conductive plating base layer contacting a top surface of the terminal pad; and a copper block on the plating base layer.

摘要翻译： 一种α粒子阻挡结构及其制造方法。 该结构包括：半导体衬底; 一组层间电介质层，从最靠近衬底的最下层的层间电介质层堆叠到距离衬底最远的最上层的层间电介质层，层间电介质层组中的每个层间电介质层包括导电线，电线的顶表面基本上 与对应的层间电介质层的顶表面共面; 接触最上面的层间电介质层的焊盘的导电的最终焊盘; 与所述端子焊盘的顶表面接触的导电电镀基层; 以及镀覆基底层上的铜块。