公开(公告)号：US20090210686A1

公开(公告)日：2009-08-20

申请号：US12032371

申请日：2008-02-15

申请人： James J. Bonanno ,  Brian R. Prasky

发明人： James J. Bonanno ,  Brian R. Prasky

IPC分类号： G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/3848

摘要： A method, system and computer product for purging pattern history tables as a function of global accuracy in a state machine-based filter gshare branch predictor. An exemplary embodiment includes a method including storing a plurality of encountered branch instructions in the branch history table, indexing the branch history table by a branch instruction address, modifying an entry of the branch history table, indexing the pattern history table, selecting at least one of a branch history entry and a pattern history table entry as a prediction for the branch instruction, wherein the pattern history table entry is selected as the prediction for the branch instruction in response to the branch history entry being in a state specifying to use the pattern history table entry, comparing a pattern history table accuracy to an accuracy threshold, and in response to the pattern history table accuracy falling below the accuracy threshold, purging the PHT.

摘要翻译： 一种用于在基于状态机的过滤器gshare分支预测器中作为全局精度的函数来清除模式历史表的方法，系统和计算机产品。 一个示例性实施例包括一种方法，包括将多个遇到的分支指令存储在分支历史表中，通过分支指令地址索引分支历史表，修改分支历史表的条目，索引模式历史表，选择至少一个 分支历史条目和模式历史表条目作为分支指令的预测，其中，响应于分支历史条目处于指定使用模式的状态，选择模式历史表条目作为用于分支指令的预测 历史表条目，将模式历史表精度与精度阈值进行比较，并且响应于模式历史表精度低于精度阈值，清除PHT。

公开(公告)号：US07082520B2

公开(公告)日：2006-07-25

申请号：US10143621

申请日：2002-05-09

申请人： James J. Bonanno ,  Brian R. Prasky

发明人： James J. Bonanno ,  Brian R. Prasky

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/42

CPC分类号： G06F9/3806 ,  G06F9/322 ,  G06F9/3848

摘要： Improved Branch prediction utilizes both a Branch Target Buffer (BTB) and a Multiple Target Table (MTT) for providing the capability to predict multiple targets for a single branch. A MTT when used in conjunction with a BTB allows for branches which have changing targets to be able to selectively choose the target of choice based on the execution path that was taken that lead to the given branch. The method predicts traget addresses, and between the static and dynamic target address, and upon finding a hit, the target is sent to the instruction cache such that a fetch can begin for the current target address and the target address is sent back to the Branch Target Buffer (BTB) to begin the search for the next branch given the current target predicted address. Upon resolving a branch the dynamic target is placed in MTT for future use.

摘要翻译： 改进的分支预测利用分支目标缓冲器（BTB）和多目标表（MTT）来提供预测单个分支的多个目标的能力。 当与BTB一起使用时，MTT允许具有变化目标的分支能够基于通过给定分支所执行的执行路径选择性地选择目标。 该方法预测traget地址以及静态目标地址和动态目标地址之间，并且在找到命中时，目标被发送到指令高速缓存，使得可以开始对当前目标地址的获取，并且目标地址被发送回到分支 目标缓冲区（BTB）开始搜索给定当前目标预测地址的下一个分支。 解析分支后，将动态目标放在MTT中以备将来使用。

公开(公告)号：US20130339596A1

公开(公告)日：2013-12-19

申请号：US13524574

申请日：2012-06-15

申请人： Brian R. Prasky ,  Anthony Saporito ,  Aaron Tsai

发明人： Brian R. Prasky ,  Anthony Saporito ,  Aaron Tsai

IPC分类号： G06F12/08

CPC分类号： G06F1/3275 ,  G06F9/3802 ,  G06F12/0864 ,  G06F17/30982 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

摘要： Embodiments of the disclosure include selectively powering up a cache set of a multi-set associative cache by receiving an instruction fetch address and determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory. Based on determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory a cache set of the multi-set associative cache that contains a cache line referenced by the instruction fetch address is identified and only powering up a subset of cache. Based on the identified cache set not being powered up, selectively powering up the identified cache set of the multi-set associative cache and transmitting one or more instructions stored in the cache line referenced by the instruction fetch address to a processor.

摘要翻译： 本公开的实施例包括通过接收指令获取地址并且确定指令获取地址对应于内容可寻址存储器的多个条目之一来选择性地加电多组关联高速缓存的高速缓存组。 基于确定指令获取地址对应于内容可寻址存储器的多个条目中的一个，识别包含由指令获取地址引用的高速缓存行的多组关联高速缓存的高速缓存集，并且仅为子集 的缓存。 基于所识别的未被加电的高速缓存集，选择性地加电多组关联高速缓存的所识别的高速缓存集，并且将由指令提取地址引用的高速缓存行中存储的一个或多个指令发送到处理器。

公开(公告)号：US10338923B2

公开(公告)日：2019-07-02

申请号：US12435631

申请日：2009-05-05

申请人： Philip G. Emma ,  Allan M. Hartstein ,  Keith N. Langston ,  Brian R. Prasky ,  Thomas R. Puzak ,  Charles F. Webb

发明人： Philip G. Emma ,  Allan M. Hartstein ,  Keith N. Langston ,  Brian R. Prasky ,  Thomas R. Puzak ,  Charles F. Webb

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/0862 ,  G06F8/41

摘要： A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address.

公开(公告)号：US10007523B2

公开(公告)日：2018-06-26

申请号：US13099178

申请日：2011-05-02

申请人： Vijayalakshmi Srinivasan ,  Brian R. Prasky

发明人： Vijayalakshmi Srinivasan ,  Brian R. Prasky

IPC分类号： G06F9/38

CPC分类号： G06F9/383 ,  G06F9/3832 ,  G06F9/3836 ,  G06F9/3844 ,  G06F9/3851

摘要： In a decode stage of hardware processor pipeline, one particular instruction of a plurality of instructions is decoded. It is determined that the particular instruction requires a memory access. Responsive to such determination, it is predicted whether the memory access will result in a cache miss. The predicting in turn includes accessing one of a plurality of entries in a pattern history table stored as a hardware table in the decode stage. The accessing is based, at least in part, upon at least a most recent entry in a global history buffer. The pattern history table stores a plurality of predictions. The global history buffer stores actual results of previous memory accesses as one of cache hits and cache misses. Additional steps include scheduling at least one additional one of the plurality of instructions in accordance with the predicting; and updating the pattern history table and the global history buffer subsequent to actual execution of the particular instruction in an execution stage of the hardware processor pipeline, to reflect whether the predicting was accurate.

公开(公告)号：US09182991B2

公开(公告)日：2015-11-10

申请号：US13366999

申请日：2012-02-06

申请人： Alper Buyuktosunoglu ,  Brian R. Prasky ,  Vijayalakshmi Srinivasan

发明人： Alper Buyuktosunoglu ,  Brian R. Prasky ,  Vijayalakshmi Srinivasan

IPC分类号： G06F9/38

CPC分类号： G06F9/3844 ,  G06F9/3851

摘要： A computer system for instruction execution includes a processor having a pipeline. The system is configured to perform a method including fetching, in the pipeline, a plurality of instructions, wherein the plurality of instructions includes a plurality of branch instructions, for each of the plurality of branch instructions, assigning a branch uncertainty to each of the plurality of branch instructions, for each of the plurality of instructions, assigning an instruction uncertainty that is a summation of branch uncertainties of older unresolved branches and balancing the instructions, based on a current summation of instruction uncertainty, in the pipeline.

摘要翻译： 用于指令执行的计算机系统包括具有流水线的处理器。 该系统被配置为执行一种方法，包括在流水线中取出多个指令，其中多个指令包括多个分支指令，对于多个分支指令中的每一个，向多个指令中的每一个指派分支不确定度 对于所述多个指令中的每一个指令，分配指示不确定性，所述指令不确定性是基于所述流水线中的指令不确定性的当前求和而作为旧的未解析分支的分支不确定性的总和并且平衡所述指令。

公开(公告)号：US09152510B2

公开(公告)日：2015-10-06

申请号：US13548448

申请日：2012-07-13

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

IPC分类号： G06F11/00 ,  G06F11/14

CPC分类号： G06F11/1479 ,  G06F11/1438

摘要： A computer system includes a simultaneous multi-threading processor and memory in operable communication with the processor. The processor is configured to perform a method including running multiple threads simultaneously, detecting a hardware error in one or more hardware structures of the processing circuit, and identifying one or more victim threads of the multiple threads. The processor is further configured to identify a plurality of hardware structures associated with execution of the one or more victim threads, isolate the one or more victim threads from the rest of the multiple threads by preventing access to the plurality of hardware structures by the multiple threads, flush the one or more victim threads by resetting hardware states of the plurality of hardware structures, and restore the one or more victim threads by restoring the plurality of hardware structures to a known safe state.

公开(公告)号：US20130332670A1

公开(公告)日：2013-12-12

申请号：US13493636

申请日：2012-06-11

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

IPC分类号： G06F12/08

CPC分类号： G06F17/30982 ,  G06F12/0817 ,  G06F12/12

摘要： Embodiments of the invention relate to process identifier (PID) based cache information transfer. An aspect of the invention includes sending, by a first core of a processor, a PID associated with a cache miss in a first local cache of the first core to a second cache of the processor. Another aspect of the invention includes determining that the PID associated with the cache miss is listed in a PID table of the second cache. Yet another aspect of the invention includes based on the PID being listed in the PID table of the second cache, determining a plurality of entries in a cache directory of the second cache that are associated with the PID. Yet another aspect of the invention includes pushing cache information associated with each of the determined plurality of entries in the cache directory from the second cache to the first local cache.

摘要翻译： 本发明的实施例涉及基于过程标识符（PID）的高速缓存信息传送。 本发明的一个方面包括由处理器的第一核心将与第一核心的第一本地高速缓存中的高速缓存未命中相关联的PID发送到处理器的第二高速缓存。 本发明的另一方面包括确定与高速缓存未命中相关联的PID被列在第二高速缓存的PID表中。 本发明的另一方面包括基于PID列在第二高速缓存的PID表中，确定与PID相关联的第二高速缓存的高速缓存目录中的多个条目。 本发明的另一方面包括将高速缓存目录中的确定的多个条目中的每一个相关联的缓存信息从第二高速缓存推送到第一本地高速缓存。

公开(公告)号：US20130191678A1

公开(公告)日：2013-07-25

申请号：US13353544

申请日：2012-01-19

申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

IPC分类号： G06F1/08

CPC分类号： G06F11/24 ,  G06F1/206 ,  G06F1/32 ,  G06F1/324

摘要： A re-characterization process is provided that adjusts one or more operating parameters of a processor to improve the health (e.g., reduce errors) of the processor. The parameters include voltage and/or clock frequency, as examples. The processor can be an inactive or active processor for which the re-characterization process is performed. It is performed, in one instance, by a hardware controller in real-time.

摘要翻译： 提供重新表征处理，其调整处理器的一个或多个操作参数以改善处理器的健康状况（例如，减少错误）。 参数包括电压和/或时钟频率，例如。 处理器可以是对其执行重新表征处理的非活动或活动处理器。 在一个实例中，它由硬件控制器实时执行。

公开(公告)号：US20110320774A1

公开(公告)日：2011-12-29

申请号：US12822379

申请日：2010-06-24

申请人： Christian Jacobi ,  Barry W. Krumm ,  Brian R. Prasky ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Charles F. Webb ,  Joshua M. Weinberg

发明人： Christian Jacobi ,  Barry W. Krumm ,  Brian R. Prasky ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Charles F. Webb ,  Joshua M. Weinberg

IPC分类号： G06F9/38

CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F9/3806 ,  G06F9/3844 ,  G06F9/3857

摘要： A system for data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.

摘要翻译： 一种用于数据操作数取出控制的系统包括一计算机处理器，该计算机处理器包括用于确定存储器访问操作的控制 控制单元被配置为执行方法。 该方法包括：计算流水线中每个指令的求和权重值，求和作为分支不确定度的函数计算的求和权重值以及相对于流水线中的其他指令，指令驻留在流水线中的挂起。 该方法还包括将尝试访问系统存储器的所选择的指令的求和权重值映射到存储器访问控制，每个存储器访问控制指定处理数据获取操作的方式。 该方法还包括基于映射执行针对所选择的指令的存储器访问操作。