利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

133 条记录 (耗时 0.027 秒)

    Delay circuit of delay locked loop having single and dual delay lines and control method of the same
    61.
    发明授权
    Delay circuit of delay locked loop having single and dual delay lines and control method of the same 有权
    具有单延迟线和双延迟线的延迟锁定环路的延迟电路及其控制方法

    公开(公告)号：US07733147B2

    公开(公告)日：2010-06-08

    申请号：US12172887

    申请日：2008-07-14

    申请人： Hyun-Woo Lee ,  Won-Joo Yun

    发明人： Hyun-Woo Lee ,  Won-Joo Yun

    IPC分类号： H03H11/26

    CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K2005/00052 ,  H03K2005/00058

    摘要： A delay circuit in a delay locked loop includes a first delay circuit unit for delaying an input signal using a single delay line in response to first control signals and then outputting a first delay signal and a second delay signal, and a second delay circuit unit for delaying the first delay signal and the second delay signal by delay time, which is correspondent to second control signals and third control signals, using a dual delay line and then outputting a third delay signal and a fourth delay signal.

    摘要翻译： 延迟锁定环路中的延迟电路包括：第一延迟电路单元，用于响应于第一控制信号使用单个延迟线延迟输入信号，然后输出第一延迟信号和第二延迟信号;以及第二延迟电路单元， 使用双延迟线延迟与第二控制信号和第三控制信号对应的延迟时间的第一延迟信号和第二延迟信号，然后输出第三延迟信号和第四延迟信号。

    Clock generator for semiconductor memory apparatus
    62.
    发明授权
    Clock generator for semiconductor memory apparatus 有权
    半导体存储装置的时钟发生器

    公开(公告)号：US07619454B2

    公开(公告)日：2009-11-17

    申请号：US12185855

    申请日：2008-08-05

    申请人： Hyun-Woo Lee

    发明人： Hyun-Woo Lee

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0814 ,  G11C7/22 ,  G11C7/222 ,  H03K2005/00241

    摘要： The clock generator for semiconductor memory apparatus which includes: a first divider configured to divide a frequency of a first internal clock generated by using an external clock; a first delay unit configured to delay an output of the first divider by first delay time; a second divider configured to divide a frequency of an output of the first delay unit; a second delay unit configured to delay the output of the second divider by second delay time; a phase comparator configured to compare a phase of the output of the first divider with a phase of the output of the second delay unit and output a result of the comparison; and a delay time setting unit configured to set the first delay time on the basis of the output of the phase comparator.

    摘要翻译： 一种用于半导体存储装置的时钟发生器，包括：第一分配器，被配置为分频通过使用外部时钟产生的第一内部时钟的频率; 第一延迟单元，被配置为将所述第一分频器的输出延迟第一延迟时间; 第二分频器，被配置为对所述第一延迟单元的输出的频率进行分频; 第二延迟单元，被配置为将所述第二分频器的输出延迟第二延迟时间; 相位比较器，被配置为将第一分频器的输出的相位与第二延迟单元的输出的相位进行比较，并输出比较结果; 以及延迟时间设定单元，被配置为基于相位比较器的输出来设定第一延迟时间。

    Delay locked loop circuit in semiconductor device and its control method
    63.
    发明授权
    Delay locked loop circuit in semiconductor device and its control method 有权
    半导体器件中的延迟锁定环路及其控制方法

    公开(公告)号：US07567102B2

    公开(公告)日：2009-07-28

    申请号：US11987935

    申请日：2007-12-06

    申请人： Hyun-Woo Lee

    发明人： Hyun-Woo Lee

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/095

    摘要： A delay locked loop (DLL) device includes a first and a second input buffers for receiving an external clock, a multiplexer for selectively outputting a first and a second internal clocks based on a most significant bit (MSB) signal, a delay means for delaying the first and the second internal clock which is selected by the multiplexer, a phase detector for comparing a phase of the first internal clock with that of a feedback clock which is feedbacked from the delay means to thereby output a comparing signal, a low pass filter (LPF) mode generator for outputting a locking signal, which checks a locking state of the feedback clock based on the comparing signal and a first and a second control signals, to the delay means, and a low pass filter for receiving the comparing signal to inform whether or not the comparing signal is erroneous to the delay means.

    摘要翻译： 延迟锁定环（DLL）装置包括用于接收外部时钟的第一和第二输入缓冲器，用于基于最高有效位（MSB）信号选择性地输出第一和第二内部时钟的多路复用器，用于延迟的延迟装置 由多路复用器选择的第一和第二内部时钟，相位检测器，用于将第一内部时钟的相位与从延迟装置反馈的反馈时钟的相位进行比较，从而输出比较信号;低通滤波器 （LPF）模式发生器，用于输出锁定信号，该锁定信号基于比较信号和第一和第二控制信号检测反馈时钟的锁定状态到延迟装置;以及低通滤波器，用于接收比较信号 通知比较信号是否对延迟装置是错误的。

    Semiconductor memory device for generating a delay locked clock in early stage
    64.
    发明授权
    Semiconductor memory device for generating a delay locked clock in early stage 有权
    用于在早期产生延迟锁定时钟的半导体存储器件

    公开(公告)号：US07557627B2

    公开(公告)日：2009-07-07

    申请号：US11715783

    申请日：2007-03-08

    申请人： Hyun-Woo Lee ,  Won-Joo Yun

    发明人： Hyun-Woo Lee ,  Won-Joo Yun

    IPC分类号： H03L7/06

    CPC分类号： G11C8/18 ,  G11C7/22 ,  G11C7/222 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/095

    摘要： A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data output timing with the system clock, a second delay locked loop configured to delay an inverse signal of the system clock by a predetermined time to thereby generate a second delay locked clock synchronizing the data output timing with the system clock, and a clock selection block configured to select one of the first and second delay locked clocks to thereby output as a reference clock for data output.

    摘要翻译： 半导体存储装置包括第一延迟锁定环，其被配置为将系统时钟延迟预定时间，从而产生使数据输出定时与系统时钟同步的第一延迟锁定时钟;第二延迟锁定环，被配置为延迟系统时钟的反相信号 系统时钟预定时间，从而产生将数据输出定时与系统时钟同步的第二延迟锁定时钟，以及配置为选择第一和第二延迟锁定时钟之一的时钟选择块，从而作为参考时钟输出 数据输出。

    System and method for CD determination using an alignment sensor of a lithographic apparatus
    65.
    发明申请
    System and method for CD determination using an alignment sensor of a lithographic apparatus 有权
    使用光刻设备的对准传感器进行CD确定的系统和方法

    公开(公告)号：US20080111995A1

    公开(公告)日：2008-05-15

    申请号：US11599619

    申请日：2006-11-15

    申请人： Hyun-Woo Lee ,  Sami Musa

    发明人： Hyun-Woo Lee ,  Sami Musa

    IPC分类号： G01B11/02

    CPC分类号： G03F7/70641 ,  G03F7/70625 ,  G03F9/7065 ,  G03F9/7076

    摘要： A system and method for determining parameters such as critical dimension of a patterned structure and best focus condition of a lithographic apparatus, based on measurment of the intensity of a non-zero order of light diffracted from an experimental structure. The experimental structure includes a first array of lines and partially filled spaces having a period longer than the wavelength of the diffracted light. The experimental structure also includes a second array of lines and spaces, where the second array of lines and spaces comprise the partially filled spaces.

    摘要翻译： 基于从实验结构衍射的光的非零级的强度的测量，确定诸如图案化结构的临界尺寸和光刻设备的最佳聚焦条件的参数的系统和方法。 实验结构包括具有比衍射光的波长长的周期的第一阵列阵列和部分填充空间。 实验结构还包括线和空间的第二阵列，其中第二阵列的线和空间构成部分填充的空间。

    Semiconductor memory apparatus
    67.
    发明申请
    Semiconductor memory apparatus 有权
    半导体存储装置

    公开(公告)号：US20080079470A1

    公开(公告)日：2008-04-03

    申请号：US11824428

    申请日：2007-06-29

    申请人： Won-Joo Yun ,  Hyun-Woo Lee

    发明人： Won-Joo Yun ,  Hyun-Woo Lee

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/095

    摘要： A semiconductor memory apparatus includes a delay line configured to delay a reference clock, a first delay block configured to delay a feedback clock, a first phase comparator configured to compare the reference clock with an output of the first delay block, a second delay block configured to delay the reference clock, a second phase comparator configured to compare the feedback clock with an output of the second delay block, a delay controller configured to control a delay amount of the delay line based on comparison results from the first and second phase comparators, a delay model configured to delay an output of the delay line by a modeled delay time to generate the feedback clock, and a locking detector configured to control the delay controller based on comparison results from the first and second phase comparators.

    摘要翻译： 一种半导体存储装置，包括：延迟线，被配置为延迟参考时钟;第一延迟块，被配置为延迟反馈时钟;第一相位比较器，被配置为将参考时钟与第一延迟块的输出进行比较;第二延迟块， 延迟参考时钟;第二相位比较器，被配置为将反馈时钟与第二延迟块的输出进行比较;延迟控制器，被配置为基于来自第一和第二相位比较器的比较结果来控制延迟线的延迟量， 延迟模型，被配置为延迟延迟线的输出通过建模的延迟时间以产生反馈时钟;以及锁定检测器，被配置为基于来自第一和第二相位比较器的比较结果来控制延迟控制器。

    Transmit diversity apparatus and method using two or more antennas
    69.
    发明授权
    Transmit diversity apparatus and method using two or more antennas 有权
    使用两个或多个天线的发射分集装置和方法

    公开(公告)号：US07212578B2

    公开(公告)日：2007-05-01

    申请号：US09935553

    申请日：2001-08-22

    申请人： Hyun-Woo Lee ,  Ho Kyu Choi ,  Yong-Jun Kwak ,  Sung-Jin Kim

    发明人： Hyun-Woo Lee ,  Ho Kyu Choi ,  Yong-Jun Kwak ,  Sung-Jin Kim

    IPC分类号： H04B7/02

    CPC分类号： H04B7/0669 ,  H04B7/0678

    摘要： A transmit diversity system having at least four antennas. A first adder adds a first spread signal obtained by spreading a first symbol pattern with a first orthogonal code to a second spread signal obtained by spreading the first symbol pattern with a second orthogonal code, and transmits the added signal through a first antenna. A second adder adds the first spread signal to a third spread signal obtained by spreading an inverted symbol pattern of the first symbol pattern with the second orthogonal code, and transmits the added signal through a second antenna. A third adder adds a fourth spread signal obtained by spreading a second symbol pattern with the first orthogonal code to a fifth spread signal obtained by spreading the second symbol pattern with the second orthogonal code, and transmits the added signal through a third antenna. A fourth adder adds the fourth spread signal to a sixth spread signal obtained by spreading an inverted symbol of the second symbol pattern with the second orthogonal code, and transmits the added signal through a fourth antenna.

    摘要翻译： 一种具有至少四个天线的发射分集系统。 第一加法器将通过用第一正交码扩展第一符号模式而获得的第一扩展信号加到通过用第二正交码扩展第一符号模式而获得的第二扩展信号，并通过第一天线发送相加信号。 第二加法器将第一扩展信号与通过用第二正交码扩展第一符号图案的反相符号图案而获得的第三扩展信号相加，并通过第二天线发送相加的信号。 第三加法器将通过用第一正交码扩展第二符号模式而获得的第四扩展信号加到通过用第二正交码扩展第二符号模式而获得的第五扩展信号，并通过第三天线发送相加的信号。 第四加法器将第四扩展信号与通过用第二正交码扩展第二符号模式的反相符号获得的第六扩展信号相加，并通过第四天线发送相加信号。

    Apparatus and method for synchronization of uplink synchronous transmission scheme in a CDMA communication system
    70.
    发明授权
    Apparatus and method for synchronization of uplink synchronous transmission scheme in a CDMA communication system 有权
    CDMA通信系统中上行同步传输方案的同步装置及方法

    公开(公告)号：US07120132B2

    公开(公告)日：2006-10-10

    申请号：US09888914

    申请日：2001-06-25

    申请人： Sung-Ho Choi ,  Yong-Jun Kwak ,  Kook-Heui Lee ,  Hyun-Woo Lee ,  Seong-Ill Park ,  Ho-Kyu Choi

    发明人： Sung-Ho Choi ,  Yong-Jun Kwak ,  Kook-Heui Lee ,  Hyun-Woo Lee ,  Seong-Ill Park ,  Ho-Kyu Choi

    IPC分类号： H04B7/216 ,  H04J3/06

    CPC分类号： H04W56/0005 ,  H04B1/707 ,  H04B1/7075

    摘要： Disclosed is a method for synchronizing a scrambling code in a CDMA communication system including a UTRAN (UMTS Terrestrial Radio Access Network) and a plurality of user equipments (UEs), using orthogonal codes for identifying the UEs and a single scrambling code for identifying the UTRAN by the UEs, and employing an uplink synchronous transmission scheme (USTS) where the UEs synchronize frames of uplink dedicated physical channels (DPCHs) using the single scrambling code. The UEs receive a reference signal including reference time information provided from the UTRAN and transmit a random access channel (RACH) based on the reference time. The UTRAN receives the random access channels from the UEs to measure a propagation delay time (PD) of each random access channel signal from the UEs, and transmits a transmission time adjustment value calculated using the measured propagation delay time and a time offset τDPCH,n between a transmission time point of the reference signal and a transmission time point of a downlink DPCH. Each UE determines a transmission time of the uplink DPCH by receiving the transmission time adjustment value, and scrambles a message with the orthogonal code and a scrambling code generated at the reference time, at the transmission time so determined as to transmit the message over the uplink DPCH.

    摘要翻译： 公开了一种使用包括UTRAN（UMTS陆地无线电接入网）和多个用户设备（UE）的CDMA通信系统中的扰码进行同步的方法，使用用于识别UE的正交码和用于识别UTRAN的单个扰码 并且使用上行链路同步传输方案（USTS），其中UE使用单个扰码来同步上行链路专用物理信道（DPCH）的帧。 UE接收包括从UTRAN提供的参考时间信息的参考信号，并且基于参考时间发送随机接入信道（RACH）。 UTRAN从UE接收随机接入信道以测量来自UE的每个随机接入信道信号的传播延迟时间（PD），并且发送使用测量的传播延迟时间和时间偏移τ DPCH，n参考信号的传输时间点与下行链路DPCH的传输时间点之间。 每个UE通过接收传输时间调整值来确定上行链路DPCH的传输时间，并且在传输时刻在正确码和在参考时间产生的扰码进行加扰，从而确定为通过上行链路发送消息 DPCH。