公开(公告)号：US07125496B2

公开(公告)日：2006-10-24

申请号：US10166421

申请日：2002-06-10

申请人： Sung-Kwon Lee

发明人： Sung-Kwon Lee

IPC分类号： H01L21/00 ,  B44C1/22

CPC分类号： H01L21/31144 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/312 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76897

摘要： A method of etching is disclosed using a photoresist etch barrier formed by an exposure with a light source of which wavelength is in the range of 157 nm to 193 nm, such as an argon fluoride(ArF) laser or fluorine laser(F2 laser), the method includes the steps of coating a photoresist layer on a etch target layer; forming photoresist pattern by developing the photoresist layer after exposing the photoresist layer with a light source of which wavelength is in the range of 157 nm to 193 nm; forming a polymer layer and etching a portion of the etch target layer simultaneously with a mixture of fluorine-based gas, an Ar gas and an O2 gas, wherein the fluorine-based gas is CxFy or CaHbFc, and wherein x, y, a, b and c range from 1 to 10, respectively; and etching the etch target layer using the polymer layer and the photoresist pattern as the etch mask.

摘要翻译： 公开了一种蚀刻方法，其中使用光致抗蚀剂蚀刻屏障，其通过用波长在157nm至193nm范围内的光源进行曝光而形成，例如氩氟化物（ArF）激光或氟激光（F < 2激光），该方法包括以下步骤：在蚀刻目标层上涂覆光致抗蚀剂层; 通过在波长在157nm至193nm范围内的光源曝光光致抗蚀剂层之后，通过显影光致抗蚀剂层来形成光致抗蚀剂图案; 形成聚合物层并与氟基气体，Ar气体和O 2气体的混合物同时蚀刻蚀刻目标层的一部分，其中氟基气体为C < 或者其中x，y，a，b，c，c， ，b和c分别为1〜10; 并使用聚合物层和光致抗蚀剂图案作为蚀刻掩模蚀刻蚀刻目标层。

公开(公告)号：US07119013B2

公开(公告)日：2006-10-10

申请号：US10925856

申请日：2004-08-24

申请人： Min-Suk Lee ,  Tae-Woo Jung ,  Sung-Kwon Lee

发明人： Min-Suk Lee ,  Tae-Woo Jung ,  Sung-Kwon Lee

IPC分类号： H01L21/28

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888 ,  Y10S438/952

摘要： A method for fabricating a semiconductor device capable of preventing a hard mask from being lifted and patterns from being defective. Particularly, an inter-layer insulation layer and an etch stop layer formed on a substrate structure provided with conductive structures are first planarized. Then, a hard mask made of a nitride-based material is formed by using a photoresist pattern and an anti-reflective coating layer as an etch mask. After the hard mask formation, the photoresist pattern and the anti-reflective coating layer are removed. Subsequently, a SAC etching process is performed to etch the inter-layer insulation layer with use of the hard mask as an etch mask, thereby obtaining a contact hole exposing the etch stop layer disposed between the conductive structures. The exposed etch stop layer is removed through the use of a blanket etch-back process, and a cleaning process is applied thereafter.

摘要翻译： 一种制造半导体器件的方法，该半导体器件能够防止硬掩模被提起并且图案有缺陷。 特别地，首先将形成在设置有导电结构的基板结构上的层间绝缘层和蚀刻停止层平坦化。 然后，通过使用光致抗蚀剂图案和抗反射涂层作为蚀刻掩模来形成由氮化物基材料制成的硬掩模。 在硬掩模形成之后，去除光致抗蚀剂图案和抗反射涂层。 随后，执行SAC蚀刻工艺以使用硬掩模作为蚀刻掩模蚀刻层间绝缘层，从而获得暴露出设置在导电结构之间的蚀刻停止层的接触孔。 通过使用橡皮布回蚀工艺去除暴露的蚀刻停止层，此后施加清洁工艺。

公开(公告)号：US20060124587A1

公开(公告)日：2006-06-15

申请号：US11347079

申请日：2006-02-02

申请人： Sung-Kwon Lee

发明人： Sung-Kwon Lee

IPC分类号： C23F1/00 ,  H01L21/461 ,  B44C1/22 ,  C03C25/68

CPC分类号： C23F1/02 ,  C23F1/38 ,  C23F4/00 ,  H01L21/0275 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/32139

摘要： A method for fabricating a conducting layer pattern using a hard mask of which a upper surface is flattened by the use of ArF exposure light source. The method includes the steps of: forming a conducting layer on a semiconductor substrate; forming a first hard mask layer, a second hard mask layer and a third hard mask layer on the conducting layer in order; forming a photoresist pattern on the third hard mask layer using an ArF exposure light source in order to form a predetermined pattern; forming a first hard mask pattern by etching the third hard mask layer using the photoresist pattern as an etching mask; forming a second hard mask pattern by etching the second hard mask layer using the first hard mask pattern as an etching mask; removing the first hard mask pattern; and etching the first hard mask layer and the conducting layer using the second hard mask pattern as an etching mask and forming a stacked hard mask pattern having the conducting layer and the second and first hard mask patterns, whereby a spire-shaped pattern is removed from the stacked hard mask pattern.

公开(公告)号：US20060073699A1

公开(公告)日：2006-04-06

申请号：US11154473

申请日：2005-06-17

申请人： Sung-Kwon Lee ,  Min-Suk Lee

发明人： Sung-Kwon Lee ,  Min-Suk Lee

IPC分类号： H01L21/4763 ,  H01L21/31

CPC分类号： H01L21/76897

摘要： Disclosed is a method for fabricating a semiconductor device. The method includes the steps of: forming a plurality of conductive patterns on a substrate; depositing an insulation layer on the substrate; recessing the insulation layer until a vertical height of the insulation layer becomes lower than that of the plurality of conductive patterns; forming an etch stop layer in the form of sidewalls of the conductive patterns; forming a mask pattern over the etch stop layer; and forming a plurality of contact holes such that etch profiles of the plurality of contact holes are aligned with the plurality of conductive patterns and the substrate is exposed by etching the insulation layer by using the mask pattern as an etch mask.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括以下步骤：在衬底上形成多个导电图案; 在衬底上沉积绝缘层; 使绝缘层凹陷，直到绝缘层的垂直高度变得低于多个导电图案的垂直高度; 形成导电图案的侧壁形式的蚀刻停止层; 在所述蚀刻停止层上形成掩模图案; 以及形成多个接触孔，使得多个接触孔的蚀刻轮廓与多个导电图案对准，并且通过使用掩模图案作为蚀刻掩模通过蚀刻绝缘层来暴露基板。

公开(公告)号：US20060046489A1

公开(公告)日：2006-03-02

申请号：US11260392

申请日：2005-10-28

申请人： Sung-Kwon Lee

发明人： Sung-Kwon Lee

IPC分类号： H01L21/302

CPC分类号： H01L27/10885 ,  H01L27/10894 ,  H01L27/10897

摘要： The present invention provides a semiconductor memory device capable of preventing bridge formations in a peripheral circuit region and improving a process margin and a method for fabricating the same. The semiconductor memory device includes: a cell region; a peripheral circuit region adjacent to the cell region; and a plurality of line patterns formed in the cell region and the peripheral circuit region, wherein a spacing distance between the line patterns is at least onefold greater than a width of the line pattern.

摘要翻译： 本发明提供一种半导体存储器件，其能够防止外围电路区域中的桥接形成，并提高工艺余量及其制造方法。 半导体存储器件包括：单元区域; 与所述单元区域相邻的外围电路区域; 以及形成在单元区域和外围电路区域中的多个线图案，其中线图案之间的间隔距离比线图案的宽度至少大一倍。

公开(公告)号：US06994949B2

公开(公告)日：2006-02-07

申请号：US10066849

申请日：2002-02-04

申请人： Sung-Kwon Lee ,  Sang-Ik Kim

发明人： Sung-Kwon Lee ,  Sang-Ik Kim

IPC分类号： G03F7/16 ,  G03F7/40 ,  G01L21/027 ,  G01L21/283 ,  G01L21/311

CPC分类号： H01L21/76829 ,  H01L21/7681

摘要： A dual damascene process is disclosed which reduces capacitance increases caused by excess and unnecessary remnants of an etching stop layer and which also improves multi-level interconnect structures by removing the etching stop layer except for a portion that surrounds the via hole. This reduces or eliminates capacitance increase and avoids erosion of underlying interlayer insulating layers during formation of an upper, wider trench.

摘要翻译： 公开了一种双镶嵌工艺，其减少了由于蚀刻停止层的过量和不必要的残余物引起的电容增加，并且除了除了围绕通孔的部分之外，还通过除去蚀刻停止层来改善多层互连结构。 这减少或消除了电容增加，并避免了在形成上部更宽的沟槽期间下层层间绝缘层的侵蚀。

公开(公告)号：US06916733B2

公开(公告)日：2005-07-12

申请号：US10660299

申请日：2003-09-11

申请人： Sung-Kwon Lee

发明人： Sung-Kwon Lee

IPC分类号： H01L21/28 ,  H01L21/20 ,  H01L21/60 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L24/02 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76879 ,  H01L21/76897 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/05042

摘要： The method forming a contact pad of a semiconductor device, including forming a plurality of conductive layer patterns displaced on a silicon substrate with adjoining to each other; forming an insulating layer on a top of the conductive layer patterns; depositing a material layer serving as a hard mask on the insulating layer; forming a photoresist pattern between the conductive layer patterns on the hard mask material layer to form a contact hole; defining an area for forming a contact by forming by etching the hard mask material layer with utilizing the photoresist pattern as an etching mask; removing the photoresist pattern; exposing the silicon substrate by etching the insulating layer with utilizing the hard mask as an etching mask to thereby form an open portion; forming a polymer layer on the open portion; exposing the silicon substrate by removing the hard mask and the polymer layer by implementing an etch back process; and forming a contacted pad on the exposed silicon substrate.

摘要翻译： 该方法形成半导体器件的接触焊盘，包括形成在硅衬底上彼此相邻位移的多个导电层图案; 在导电层图案的顶部上形成绝缘层; 在绝缘层上沉积用作硬掩模的材料层; 在所述硬掩模材料层上的所述导电层图案之间形成光致抗蚀剂图案以形成接触孔; 通过利用光致抗蚀剂图案作为蚀刻掩模通过蚀刻硬掩模材料层而形成接触形成区域; 去除光致抗蚀剂图案; 通过利用硬掩模作为蚀刻掩模蚀刻绝缘层来暴露硅衬底，从而形成开口部分; 在开口部分上形成聚合物层; 通过实施回蚀工艺去除硬掩模和聚合物层来暴露硅衬底; 以及在暴露的硅衬底上形成接触焊盘。

公开(公告)号：US20050136642A1

公开(公告)日：2005-06-23

申请号：US10879733

申请日：2004-06-30

申请人： Sung-Kwon Lee ,  Tae-Woo Jung

发明人： Sung-Kwon Lee ,  Tae-Woo Jung

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L29/00

CPC分类号： H01L21/76897 ,  H01L21/02052 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76829 ,  Y10S438/97

摘要： Disclosed is a method for fabricating a semiconductor device with an improved process margin obtained by preventing damage to an inter-layer insulation layer during a wet cleaning process. Particularly, the method includes the steps of: forming a plurality of a first conductive pattern having a stack pattern of a first conductive and a first hard mask; forming a first inter-layer insulation layer of a good gap-fill property with a height between the first conductive material and the first hard mask on the first conductive layer; forming a second inter-layer insulation layer; forming a second conductive layer contacted the first conductive layer between the plurality of the first conductive patterns as passing through the first and the second inter-layer insulation layers; forming a third inter-layer insulation layer; forming a plurality of second conductive patterns; forming a fourth inter-layer insulation layer; and forming a third conductive layer contacted to the second conductive layer.

摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件具有通过在湿式清洗过程中防止对层间绝缘层的损坏而获得的改进的工艺余量。 特别地，该方法包括以下步骤：形成具有第一导电层和第一硬掩模的堆叠图案的多个第一导电图案; 形成第一导电层上第一导电材料与第一硬掩模之间的高度的良好间隙填充性能的第一层间绝缘层; 形成第二层间绝缘层; 形成第二导电层，所述第二导电层与所述多个所述第一导电图案之间的所述第一导电层接触通过所述第一和第二层间绝缘层; 形成第三层间绝缘层; 形成多个第二导电图案; 形成第四层间绝缘层; 以及形成与所述第二导电层接触的第三导电层。

公开(公告)号：US20050118829A1

公开(公告)日：2005-06-02

申请号：US10878289

申请日：2004-06-29

申请人： Sung-Kwon Lee ,  Min-Suk Lee

发明人： Sung-Kwon Lee ,  Min-Suk Lee

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/302 ,  H01L21/311 ,  H01L21/60

CPC分类号： H01L21/31138 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76897

摘要： Disclosed is a method for fabricating a semiconductor device having at least one contact holes formed by employing a self-aligned contact (SAC) etching process. The contact holes are formed through the shortened number of sequential steps by using different process recipes. First, an anti-reflective coating (ARC) layer formed on a substrate structure prepared sequentially with a substrate, conductive structures, an etch stop layer and an inter-layer insulation layer is etched by employing an etch gas of CF4, O2, CO and Ar. Then, a portion of an inter-layer insulation layer is etched with use of an etch gas of CF4 and O2. The rest portion of the inter-layer insulation layer is subsequently etched by using a different etch gas of C4F6, CH2F2, O2 and Ar to thereby form at least one contact hole exposing the etch stop layer.

摘要翻译： 公开了一种制造具有通过采用自对准接触（SAC）蚀刻工艺形成的至少一个接触孔的半导体器件的方法。 通过使用不同的工艺配方，通过缩短的顺序步骤形成接触孔。 首先，通过使用CF 4的蚀刻气体蚀刻形成在依次由衬底，导电结构，蚀刻停止层和层间绝缘层制备的衬底结构上的抗反射涂层（ARC）层， CO 2，CO 2和CO 2。 然后，使用CF 4 O 3和O 2 2的蚀刻气体蚀刻层间绝缘层的一部分。 随后通过使用不同的C 4 F 6 C CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 3 SUB 2，O 2 2和Ar，从而形成暴露蚀刻停止层的至少一个接触孔。

公开(公告)号：US06897159B1

公开(公告)日：2005-05-24

申请号：US10878289

申请日：2004-06-29

申请人： Sung-Kwon Lee ,  Min-Suk Lee

发明人： Sung-Kwon Lee ,  Min-Suk Lee

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/302 ,  H01L21/311 ,  H01L21/60

CPC分类号： H01L21/31138 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76897

摘要： Disclosed is a method for fabricating a semiconductor device having at least one contact holes formed by employing a self-aligned contact (SAC) etching process. The contact holes are formed through the shortened number of sequential steps by using different process recipes. First, an anti-reflective coating (ARC) layer formed on a substrate structure prepared sequentially with a substrate, conductive structures, an etch stop layer and an inter-layer insulation layer is etched by employing an etch gas of CF4, O2, CO and Ar. Then, a portion of an inter-layer insulation layer is etched with use of an etch gas of CF4 and O2. The rest portion of the inter-layer insulation layer is subsequently etched by using a different etch gas of C4F6, CH2F2, O2 and Ar to thereby form at least one contact hole exposing the etch stop layer.

摘要翻译： 公开了一种制造具有通过采用自对准接触（SAC）蚀刻工艺形成的至少一个接触孔的半导体器件的方法。 通过使用不同的工艺配方，通过缩短的顺序步骤形成接触孔。 首先，通过使用CF 4的蚀刻气体蚀刻形成在依次由衬底，导电结构，蚀刻停止层和层间绝缘层制备的衬底结构上的抗反射涂层（ARC）层， CO 2，CO 2和CO 2。 然后，使用CF 4 O 3和O 2 2的蚀刻气体蚀刻层间绝缘层的一部分。 随后通过使用不同的C 4 F 6 C CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH 3 SUB 2，O 2 2和Ar，从而形成暴露蚀刻停止层的至少一个接触孔。