公开(公告)号：US20050272173A1

公开(公告)日：2005-12-08

申请号：US11020599

申请日：2004-12-21

申请人： Sung-Kwon Lee ,  Tae-Woo Jung ,  Min-Suk Lee

发明人： Sung-Kwon Lee ,  Tae-Woo Jung ,  Min-Suk Lee

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is a method for testing a contact open capable of effectively testing a contact open defect in an In-line as securing a mass productivity. The method includes the steps of: performing a photolithography process for forming a contact; forming a contact hole by performing a contact etching process after sampling at least one wafer; depositing a conductive layer on the wafer provided with the contact hole; isolating the conductive layer within the contact hole; performing a test for testing a contact open interface to check whether a remaining layer is existed in an interface between the conductive layer and a lower structure of the conductive layer; and performing a process for etching the contact of a main lot based on a test result.

摘要翻译： 本发明是一种用于测试接触开口的方法，其能够有效地测试在线的接触开口缺陷以确保批量生产率。 该方法包括以下步骤：执行用于形成接触的光刻工艺; 在对至少一个晶片取样之后进行接触蚀刻工艺形成接触孔; 在设置有接触孔的晶片上沉积导电层; 隔离接触孔内的导电层; 执行用于测试接触开放界面的测试以检查导电层和导电层的下部结构之间的界面中是否存在剩余层; 并且基于测试结果执行蚀刻主批次的接触的处理。

公开(公告)号：US20050136683A1

公开(公告)日：2005-06-23

申请号：US10866968

申请日：2004-06-15

申请人： Sung-Kwon Lee ,  Tae-Woo Jung

发明人： Sung-Kwon Lee ,  Tae-Woo Jung

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/7684 ,  H01L21/76897

摘要： Disclosed is a method for fabricating a semiconductor device without damaging a hard mask of a conductive structure. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer and a hard mask; sequentially forming a first nitride layer, an oxide layer, a second nitride layer, and an etch stop layer on the plurality of conductive structures; forming an inter-layer insulation layer on the etch stop layer; removing a portion of the inter-layer insulation layer through a planarization process; performing a self-aligned etching (SAC) process selectively etching the inter-layer insulation layer, the second nitride layer and the oxide layer until the SAC etching process is stopped at the first nitride layer to thereby form a contact hole exposing the first nitride layer; and removing the first nitride layer by performing a blanket etch-back process to thereby expose the conductive layer.

摘要翻译： 公开了一种用于制造半导体器件而不损坏导电结构的硬掩模的方法。 该方法包括以下步骤：在衬底上形成多个导电结构，每个导电结构包括导电层和硬掩模; 在所述多个导电结构上依次形成第一氮化物层，氧化物层，第二氮化物层和蚀刻停止层; 在所述蚀刻停止层上形成层间绝缘层; 通过平坦化处理去除层间绝缘层的一部分; 执行自对准蚀刻（SAC）工艺，选择性地蚀刻层间绝缘层，第二氮化物层和氧化物层，直到在第一氮化物层处停止SAC蚀刻工艺，从而形成暴露第一氮化物层的接触孔 ; 以及通过执行覆盖层回蚀工艺去除所述第一氮化物层，从而暴露所述导电层。

公开(公告)号：US07138340B2

公开(公告)日：2006-11-21

申请号：US10866968

申请日：2004-06-15

申请人： Sung-Kwon Lee ,  Tae-Woo Jung

发明人： Sung-Kwon Lee ,  Tae-Woo Jung

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/7684 ,  H01L21/76897

摘要： Disclosed is a method for fabricating a semiconductor device without damaging a hard mask of a conductive structure. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer and a hard mask; sequentially forming a first nitride layer, an oxide layer, a second nitride layer, and an etch stop layer on the plurality of conductive structures; forming an inter-layer insulation layer on the etch stop layer; removing a portion of the inter-layer insulation layer through a planarization process; performing a self-aligned etching (SAC) process selectively etching the inter-layer insulation layer, the second nitride layer and the oxide layer until the SAC etching process is stopped at the first nitride layer to thereby form a contact hole exposing the first nitride layer; and removing the first nitride layer by performing a blanket etch-back process to thereby expose the conductive layer.

摘要翻译： 公开了一种用于制造半导体器件而不损坏导电结构的硬掩模的方法。 该方法包括以下步骤：在衬底上形成多个导电结构，每个导电结构包括导电层和硬掩模; 在所述多个导电结构上依次形成第一氮化物层，氧化物层，第二氮化物层和蚀刻停止层; 在所述蚀刻停止层上形成层间绝缘层; 通过平坦化处理去除层间绝缘层的一部分; 执行自对准蚀刻（SAC）工艺，选择性地蚀刻层间绝缘层，第二氮化物层和氧化物层，直到在第一氮化物层处停止SAC蚀刻工艺，从而形成暴露第一氮化物层的接触孔 ; 以及通过执行覆盖层回蚀工艺去除所述第一氮化物层，从而暴露所述导电层。

公开(公告)号：US20060022344A1

公开(公告)日：2006-02-02

申请号：US11143139

申请日：2005-06-01

申请人： Sung-Kwon Lee ,  Tae-Woo Jung

发明人： Sung-Kwon Lee ,  Tae-Woo Jung

IPC分类号： H01L23/52

CPC分类号： H01L27/10852 ,  H01L28/40

摘要： Disclosed are a semiconductor device with a three-dimensional storage node and a method for fabricating the same. The semiconductor device includes: an inter-layer insulation layer formed on a substrate; a first plug contacted to the substrate by penetrating into the inter-layer insulation layer; an insulation layer formed on the first plug; a second plug contacted to the first plug by penetrating into the insulation layer and projected in an upward direction from a surface level of the insulation layer; a barrier layer formed on the second plug and the insulation layer; and a storage node formed on the second plug to be connected with the second plug through a portion where the barrier layer is removed.

摘要翻译： 公开了具有三维存储节点的半导体器件及其制造方法。 半导体器件包括：形成在衬底上的层间绝缘层; 通过渗入层间绝缘层而与基板接触的第一插塞; 形成在所述第一插头上的绝缘层; 通过穿透绝缘层并从绝缘层的表面水平向上方向突出地与第一插塞接触的第二插头; 形成在所述第二插头和所述绝缘层上的阻挡层; 以及形成在第二插头上以通过去除阻挡层的部分与第二插头连接的存储节点。

公开(公告)号：US20050280035A1

公开(公告)日：2005-12-22

申请号：US11029783

申请日：2004-12-21

申请人： Sung-Kwon Lee ,  Tae-Woo Jung

发明人： Sung-Kwon Lee ,  Tae-Woo Jung

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/60 ,  H01L21/82 ,  H01L21/8242 ,  H01L29/45

CPC分类号： H01L21/76897 ,  H01L21/31144 ,  H01L27/10855

摘要： Disclosed are a semiconductor device and a method for fabricating the same capable of preventing a bridge generation between plugs during forming a plurality of hole type contact plugs for forming storage nodes. The semiconductor device includes: a first gate structure and a second gate structure placed in parallel by a predetermined space; a plurality of bit lines placed on upper portions of the first gate structure and the second gate structure with crossing the first gate structure and the second gate structure; a first cell contact plug and a second cell contact plug located through the plurality of bit lines and formed between the first gate structure and the second gate structure; and an inter-layer insulation layer provided with a first storage node contact hole and a second storage node contact hole connected with each other by etching the inter-layer insulation layer on upper portions of the plurality of bit lines.

摘要翻译： 公开了一种半导体器件及其制造方法，能够在形成用于形成存储节点的多个孔型接触插塞时，防止插塞之间的桥接产生。 半导体器件包括：第一栅极结构和第二栅极结构，其被预定空间平行放置; 放置在与第一栅极结构和第二栅极结构相交的第一栅极结构和第二栅极结构的上部上的多个位线; 位于所述多个位线之间并形成在所述第一栅极结构和所述第二栅极结构之间的第一单元接触插塞和第二单元接触插塞; 以及通过蚀刻多个位线的上部的层间绝缘层而设置有彼此连接的第一存储节点接触孔和第二存储节点接触孔的层间绝缘层。

公开(公告)号：US20050090055A1

公开(公告)日：2005-04-28

申请号：US10925856

申请日：2004-08-24

申请人： Min-Suk Lee ,  Tae-Woo Jung ,  Sung-Kwon Lee

发明人： Min-Suk Lee ,  Tae-Woo Jung ,  Sung-Kwon Lee

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888 ,  Y10S438/952

摘要： A method for fabricating a semiconductor device capable of preventing a hard mask from being lifted and patterns from being defective. Particularly, an inter-layer insulation layer and an etch stop layer formed on a substrate structure provided with conductive structures are first planarized. Then, a hard mask made of a nitride-based material is formed by using a photoresist pattern and an anti-reflective coating layer as an etch mask. After the hard mask formation, the photoresist pattern and the anti-reflective coating layer are removed. Subsequently, a SAC etching process is performed to etch the inter-layer insulation layer with use of the hard mask as an etch mask, thereby obtaining a contact hole exposing the etch stop layer disposed between the conductive structures. The exposed etch stop layer is removed through the use of a blanket etch-back process, and a cleaning process is applied thereafter.

摘要翻译： 一种制造半导体器件的方法，该半导体器件能够防止硬掩模被提起并且图案有缺陷。 特别地，首先将形成在设置有导电结构的基板结构上的层间绝缘层和蚀刻停止层平坦化。 然后，通过使用光致抗蚀剂图案和抗反射涂层作为蚀刻掩模来形成由氮化物基材料制成的硬掩模。 在硬掩模形成之后，去除光致抗蚀剂图案和抗反射涂层。 随后，执行SAC蚀刻工艺以使用硬掩模作为蚀刻掩模蚀刻层间绝缘层，从而获得暴露出设置在导电结构之间的蚀刻停止层的接触孔。 通过使用橡皮布回蚀工艺去除暴露的蚀刻停止层，此后施加清洁工艺。

公开(公告)号：US07119013B2

公开(公告)日：2006-10-10

申请号：US10925856

申请日：2004-08-24

申请人： Min-Suk Lee ,  Tae-Woo Jung ,  Sung-Kwon Lee

发明人： Min-Suk Lee ,  Tae-Woo Jung ,  Sung-Kwon Lee

IPC分类号： H01L21/28

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888 ,  Y10S438/952

摘要： A method for fabricating a semiconductor device capable of preventing a hard mask from being lifted and patterns from being defective. Particularly, an inter-layer insulation layer and an etch stop layer formed on a substrate structure provided with conductive structures are first planarized. Then, a hard mask made of a nitride-based material is formed by using a photoresist pattern and an anti-reflective coating layer as an etch mask. After the hard mask formation, the photoresist pattern and the anti-reflective coating layer are removed. Subsequently, a SAC etching process is performed to etch the inter-layer insulation layer with use of the hard mask as an etch mask, thereby obtaining a contact hole exposing the etch stop layer disposed between the conductive structures. The exposed etch stop layer is removed through the use of a blanket etch-back process, and a cleaning process is applied thereafter.

摘要翻译： 一种制造半导体器件的方法，该半导体器件能够防止硬掩模被提起并且图案有缺陷。 特别地，首先将形成在设置有导电结构的基板结构上的层间绝缘层和蚀刻停止层平坦化。 然后，通过使用光致抗蚀剂图案和抗反射涂层作为蚀刻掩模来形成由氮化物基材料制成的硬掩模。 在硬掩模形成之后，去除光致抗蚀剂图案和抗反射涂层。 随后，执行SAC蚀刻工艺以使用硬掩模作为蚀刻掩模蚀刻层间绝缘层，从而获得暴露出设置在导电结构之间的蚀刻停止层的接触孔。 通过使用橡皮布回蚀工艺去除暴露的蚀刻停止层，此后施加清洁工艺。

公开(公告)号：US20050136642A1

公开(公告)日：2005-06-23

申请号：US10879733

申请日：2004-06-30

申请人： Sung-Kwon Lee ,  Tae-Woo Jung

发明人： Sung-Kwon Lee ,  Tae-Woo Jung

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L29/00

CPC分类号： H01L21/76897 ,  H01L21/02052 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76829 ,  Y10S438/97

摘要： Disclosed is a method for fabricating a semiconductor device with an improved process margin obtained by preventing damage to an inter-layer insulation layer during a wet cleaning process. Particularly, the method includes the steps of: forming a plurality of a first conductive pattern having a stack pattern of a first conductive and a first hard mask; forming a first inter-layer insulation layer of a good gap-fill property with a height between the first conductive material and the first hard mask on the first conductive layer; forming a second inter-layer insulation layer; forming a second conductive layer contacted the first conductive layer between the plurality of the first conductive patterns as passing through the first and the second inter-layer insulation layers; forming a third inter-layer insulation layer; forming a plurality of second conductive patterns; forming a fourth inter-layer insulation layer; and forming a third conductive layer contacted to the second conductive layer.

摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件具有通过在湿式清洗过程中防止对层间绝缘层的损坏而获得的改进的工艺余量。 特别地，该方法包括以下步骤：形成具有第一导电层和第一硬掩模的堆叠图案的多个第一导电图案; 形成第一导电层上第一导电材料与第一硬掩模之间的高度的良好间隙填充性能的第一层间绝缘层; 形成第二层间绝缘层; 形成第二导电层，所述第二导电层与所述多个所述第一导电图案之间的所述第一导电层接触通过所述第一和第二层间绝缘层; 形成第三层间绝缘层; 形成多个第二导电图案; 形成第四层间绝缘层; 以及形成与所述第二导电层接触的第三导电层。

公开(公告)号：US20060246730A1

公开(公告)日：2006-11-02

申请号：US11321591

申请日：2005-12-30

申请人： Myung-Ok Kim ,  Tae-Woo Jung ,  Sung-Kwon Lee ,  Sea-Ug Jang

发明人： Myung-Ok Kim ,  Tae-Woo Jung ,  Sung-Kwon Lee ,  Sea-Ug Jang

IPC分类号： H01L21/311

CPC分类号： H01L21/31116 ,  H01L29/66621

摘要： A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to form a plurality of recess structures each of which has a flat bottom portion with a critical dimension (CD) larger than that of a top portion; and sequentially forming a gate oxide layer and a metal layer on the recess structures; and patterning the gate oxide layer and the metal layer to form a plurality of gate structures.

摘要翻译： 提供一种制造半导体器件的晶体管的方法。 该方法包括：在包括底部结构的衬底中形成器件隔离层，从而限定有源区; 将活性区域蚀刻到预定深度以形成多个凹部结构，每个凹部结构具有平坦的底部，其临界尺寸（CD）大于顶部部分的临界尺寸; 并且在所述凹部结构上依次形成栅极氧化物层和金属层; 以及图案化栅极氧化物层和金属层以形成多个栅极结构。

公开(公告)号：US07405091B2

公开(公告)日：2008-07-29

申请号：US11020599

申请日：2004-12-21

申请人： Sung-Kwon Lee ,  Tae-Woo Jung ,  Min-Suk Lee

发明人： Sung-Kwon Lee ,  Tae-Woo Jung ,  Min-Suk Lee

IPC分类号： G01R31/26 ,  H01L21/66

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is a method for testing a contact open capable of effectively testing a contact open defect in an In-line as securing a mass productivity. The method includes the steps of: performing a photolithography process for forming a contact; forming a contact hole by performing a contact etching process after sampling at least one wafer; depositing a conductive layer on the wafer provided with the contact hole; isolating the conductive layer within the contact hole; performing a test for testing a contact open interface to check whether a remaining layer is existed in an interface between the conductive layer and a lower structure of the conductive layer; and performing a process for etching the contact of a main lot based on a test result.

摘要翻译： 本发明是一种用于测试接触开口的方法，其能够有效地测试在线的接触开口缺陷以确保批量生产率。 该方法包括以下步骤：执行用于形成接触的光刻工艺; 在对至少一个晶片取样之后进行接触蚀刻工艺形成接触孔; 在设置有接触孔的晶片上沉积导电层; 隔离接触孔内的导电层; 执行用于测试接触开放界面的测试以检查导电层和导电层的下部结构之间的界面中是否存在剩余层; 并且基于测试结果执行蚀刻主批次的接触的处理。