公开(公告)号：US5824892A

公开(公告)日：1998-10-20

申请号：US899048

申请日：1997-07-23

申请人： Yasushi Ishii

发明人： Yasushi Ishii

IPC分类号： G01F17/00 ,  G01F22/02

CPC分类号： G01F17/00

摘要： An acoustic device for measuring volume difference between a standard object and an object to be measured comprises a reference container, a measuring container connected to the reference container via a separator, a loudspeaker provided at the separator, for cyclically provides complementary variations in volume to these two containers, microphones for detecting pressure variations inside these respective containers, and a signal processor for measuring a ratio between the magnitude of the detected pressure variation inside the reference container and the magnitude of the detected pressure variation inside the measuring container, and obtaining a difference in volume between the object to be measured and the standard object from the measured ratio when the standard object is placed into the measuring container and the measured ratio when the object to be measured is placed into the measuring container.

摘要翻译： 用于测量标准物体和被测量物体之间的体积差异的声学装置包括参考容器，经由分离器连接到参考容器的测量容器，设置在分离器处的扬声器，用于循环地向这些容器提供体积的互补变化 用于检测这些各个容器内的压力变化的两个容器，麦克风和用于测量参考容器内检测到的压力变化的大小与测量容器内检测到的压力变化的大小之间的比率的信号处理器， 当将标准物体放入测量容器中时，测量对象与标准物体之间的体积与被测量的比例以及待测量对象被放置在测量容器中时的测量比。

公开(公告)号：US5218679A

公开(公告)日：1993-06-08

申请号：US662172

申请日：1991-02-28

申请人： Jun Hasegawa ,  Yutaka Aoyama ,  Yasushi Ishii

发明人： Jun Hasegawa ,  Yutaka Aoyama ,  Yasushi Ishii

IPC分类号： H05K7/10 ,  H05K7/14

CPC分类号： H05K7/1468 ,  H05K7/1092 ,  G05B2219/1176 ,  G05B2219/15078

摘要： A programmable controller with an I/O signal converting circuit having an input element and an output element, comprises a signal I/O unit having a plurality of element sockets capable of replaceably accommodating both the input element and the output element; a selecting unit for selecting the type of the accommodated element; and a signal storing and sending unit. Each element socket may accommodate the input and output elements. Therefore, the space required to install the I/O circuits is reduced, and the number of input and output elements can be arbitrarily set.

摘要翻译： 具有输入元件和输出元件的具有I / O信号转换电路的可编程控制器包括具有能够可替代地容纳输入元件和输出元件的多个元件插座的信号I / O单元; 选择单元，用于选择所容纳的元件的类型; 和信号存储和发送单元。 每个元件插座可以容纳输入和输出元件。 因此，安装I / O电路所需的空间减少，输入和输出元件的数量可以任意设定。

公开(公告)号：US5052225A

公开(公告)日：1991-10-01

申请号：US481251

申请日：1990-02-20

申请人： Yasushi Ishii

发明人： Yasushi Ishii

IPC分类号： G01C19/5698

CPC分类号： G01C19/5698

摘要： An acoustic gyro comprises two vessels disposed at both sides of a single separator, at least one sensing duct coupled with these two vessels, a single sound source provided on the separator to differentially provide a volume change to the two vessels, and at least one sound detector attached to each of at least one sensing duct, wherein, when the gyro is rotated, the sound detector detects a change in the sound pressure caused by the Coriolis force at a position other than an acoustic neutral point within the sensing duct to obtain an output corresponding to an angular rate of the rotation.

摘要翻译： 声陀螺仪包括设置在单个分离器的两侧的两个容器，与这两个容器耦合的至少一个感测导管，设置在分离器上的单个声源以差分地提供对两个容器的体积变化，以及至少一个声音 检测器附接到至少一个感测通道中的每一个，其中当陀螺仪旋转时，声音检测器检测由科里奥利力在感测管道内的声中性点之外的位置引起的声压变化，以获得 输出对应于旋转的角速度。

公开(公告)号：US08633530B2

公开(公告)日：2014-01-21

申请号：US13144744

申请日：2009-10-23

申请人： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

发明人： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

IPC分类号： H01L21/28 ,  H01L29/792 ,  H01L21/336 ,  H01L27/06

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.

摘要翻译： 在存储单元（MC）的馈电区域中，在存储单元（MC）的馈电区域中，通过自对准在存储器nMIS（Qnm）的选择栅极（CG）的侧表面上提供存储器nMIS（Qnm）的侧壁形状的存储栅极（MG） 通过绝缘膜选择nMIS（Qnc），向存储栅电极（MG）提供电压的插头（PM）嵌入在形成在存储栅上的层间绝缘膜（9）中形成的接触孔（CM） 电极（MG）并且电连接到存储栅电极（MG）。 由于在选择栅电极（CG）的上表面上形成帽绝缘膜（CAP），所以可以防止插头（PM）与选择栅电极（CG）之间的导电。

公开(公告)号：US08576634B2

公开(公告)日：2013-11-05

申请号：US12764090

申请日：2010-04-20

申请人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

发明人： Fumitoshi Ito ,  Yoshiyuki Kawashima ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama ,  Yukiko Manabe

IPC分类号： G11C11/34 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

摘要翻译： 改善了具有非易失性存储元件的半导体器件的积分度和重写次数。 与第一MONOS非易失性存储元件相比，具有大门宽度的第一MONOS非易失性存储元件和第二MONOS非易失性存储元件一起安装在同一衬底上，并且第一MONOS非易失性存储元件是 用于存储几乎不被重写的程序数据，并且第二MONOS非易失性存储元件用于存储频繁重写的处理数据。

公开(公告)号：US08395203B2

公开(公告)日：2013-03-12

申请号：US12951012

申请日：2010-11-20

申请人： Hiraku Chakihara ,  Yasushi Ishii

发明人： Hiraku Chakihara ,  Yasushi Ishii

IPC分类号： H01L29/788 ,  H01L21/8238

CPC分类号： H01L21/28273 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： Over the top of a semiconductor substrate, a lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed. Over the top of the semiconductor substrate, a memory gate electrode adjacent to the lamination pattern is formed. Between the control gate electrode and the semiconductor substrate, a third insulation film for gate insulation film is formed. Between the memory gate electrode and the semiconductor substrate, and between the lamination pattern and the memory gate electrode, a fourth insulation film including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film is formed. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.

摘要翻译： 在半导体衬底的顶部上，形成了具有控制栅电极，其上的第一绝缘膜和其上的第二绝缘膜的叠层图案。 在半导体衬底的顶部上，形成与层压图案相邻的存储栅电极。 在控制栅极电极和半导体衬底之间形成第三绝缘膜用绝缘膜。 在存储栅电极和半导体衬底之间以及叠层图案和存储栅电极之间形成包括氧化硅膜，氮化硅膜和另一氧化硅膜的叠层膜的第四绝缘膜。 在与存储栅电极相邻的层叠图案侧的侧壁处，第一绝缘膜从控制栅极电极和第二绝缘膜退回，并且控制栅电极的上端角部分被倒圆。

公开(公告)号：US20120292679A1

公开(公告)日：2012-11-22

申请号：US13468992

申请日：2012-05-10

申请人： Kota FUNAYAMA ,  Hiraku Chakihara ,  Yasushi Ishii

发明人： Kota FUNAYAMA ,  Hiraku Chakihara ,  Yasushi Ishii

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L27/11563 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/1052 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11568 ,  H01L28/40 ,  H01L29/4234 ,  H01L29/66477 ,  H01L29/66833 ,  H01L29/792

摘要： A memory cell of a nonvolatile memory and a capacitive element are formed over the same semiconductor substrate. The memory cell includes a control gate electrode formed over the semiconductor substrate via a first insulating film, a memory gate electrode formed adjacent to the control gate electrode over the semiconductor substrate via a second insulating film, and the second insulating film having therein a charge storing portion. The capacitive element includes a lower electrode formed of the same layer of a silicon film as the control gate electrode, a capacity insulating film formed of the same insulating film as the second insulating film, and an upper electrode formed of the same layer of a silicon film as the memory gate electrode. The concentration of impurities of the upper electrode is higher than that of the memory gate electrode.

摘要翻译： 在相同的半导体衬底上形成非易失性存储器和电容元件的存储单元。 存储单元包括经由第一绝缘膜形成在半导体衬底上的控制栅极电极，经由第二绝缘膜在半导体衬底上与控制栅电极相邻形成的存储栅电极，并且其中具有电荷存储的第二绝缘膜 一部分。 电容元件包括由与控制栅电极相同的硅膜层形成的下电极，由与第二绝缘膜相同的绝缘膜形成的电容绝缘膜和由相同的硅层形成的上电极 薄膜作为记忆栅电极。 上部电极的杂质浓度高于记忆栅电极的浓度。

公开(公告)号：US07863135B2

公开(公告)日：2011-01-04

申请号：US12706668

申请日：2010-02-16

申请人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

发明人： Takeshi Sakai ,  Yasushi Ishii ,  Tsutomu Okazaki ,  Masaru Nakamichi ,  Toshikazu Matsui ,  Kyoya Nitta ,  Satoru Machida ,  Munekatsu Nakagawa ,  Yuichi Tsukada

IPC分类号： H01L21/00

CPC分类号： H01L27/11568 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11573

摘要： For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

摘要翻译： 为了增强具有MONOS型晶体管的非易失性半导体存储器件的高性能，非易失性半导体存储器件被提供有具有改进性能的MONOS型晶体管，其中MONOS非易失性存储器的存储单元包括控制 晶体管和存储晶体管。 控制晶体管的控制栅极包括n型多晶硅膜，并且形成在包括氧化硅膜的栅极绝缘膜上。 存储晶体管的存储栅极包括n型多晶硅膜，并设置在控制栅极的一个侧壁上。 存储器栅极包括具有低于控制栅极的薄层电阻的掺杂多晶硅膜，其包括通过将杂质离子注入未掺杂的硅膜形成的多晶硅膜。

公开(公告)号：US20100038700A1

公开(公告)日：2010-02-18

申请号：US12580289

申请日：2009-10-16

申请人： Tsutomu OKAZAKI ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

发明人： Tsutomu OKAZAKI ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC分类号： H01L29/792

CPC分类号： H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

摘要翻译： 半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极 。 第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分 第一个方向 第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

公开(公告)号：US07502257B2

公开(公告)日：2009-03-10

申请号：US11797164

申请日：2007-05-01

申请人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

发明人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC分类号： G11C11/34

CPC分类号： H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.