公开(公告)号：US08477541B2

公开(公告)日：2013-07-02

申请号：US13489977

申请日：2012-06-06

申请人： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

发明人： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

IPC分类号： G11C7/10

CPC分类号： G11C16/3459 ,  G06F3/0659 ,  G06F12/0246 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/104 ,  G11C2216/14

摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

公开(公告)号：US20120044766A1

公开(公告)日：2012-02-23

申请号：US13285099

申请日：2011-10-31

申请人： TAKESHI NAKANO ,  Hiroshi Nakamura ,  Koji Hosono

发明人： TAKESHI NAKANO ,  Hiroshi Nakamura ,  Koji Hosono

IPC分类号： G11C16/04

CPC分类号： G11C16/08

摘要： A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.

摘要翻译： 半导体存储器件包括转移电路和控制电路。 该传输电路包括一个p型MOS晶体管，其源极被施加第一电压，一个n型MOS晶体管被连接到p型MOS晶体管的漏极并且第一个电压被传输到其栅极，到 其源极施加第二电压，并且其漏极连接到负载。 控制电路使p型MOS晶体管导通和关断，并使p型MOS晶体管导通，使p型MOS晶体管将第二电压转移到负载，并且在传输期间使p型MOS晶体管转换为p型 MOS晶体管关闭，使n型MOS晶体管的栅极浮在第一电压。

公开(公告)号：US07916555B2

公开(公告)日：2011-03-29

申请号：US12252896

申请日：2008-10-16

申请人： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

发明人： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

IPC分类号： G11C7/10

CPC分类号： G11C16/3459 ,  G06F3/0659 ,  G06F12/0246 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/104 ,  G11C2216/14

摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

摘要翻译： 在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否 或者不是第二操作是可执行的。

公开(公告)号：US20080225618A1

公开(公告)日：2008-09-18

申请号：US12123157

申请日：2008-05-19

申请人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

发明人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

IPC分类号： G11C7/06

CPC分类号： G11C16/0483 ,  G11C5/145 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

摘要翻译： 非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。 控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中 在预定的阈值电平范围内。 在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。

公开(公告)号：US07123515B2

公开(公告)日：2006-10-17

申请号：US11119744

申请日：2005-05-03

申请人： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

发明人： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

IPC分类号： G11C11/34

CPC分类号： G11C16/3459 ,  G06F3/0659 ,  G06F12/0246 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/104 ,  G11C2216/14

摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

公开(公告)号：US07117296B2

公开(公告)日：2006-10-03

申请号：US11117669

申请日：2005-04-28

申请人： Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Mikito Nakabayashi ,  Koichi Kawai

发明人： Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Mikito Nakabayashi ,  Koichi Kawai

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G11C16/3463 ,  G11C16/3454 ,  G11C16/3459

摘要： A non-volatile semiconductor memory device includes a memory cell array in which electrically erasable and programmable memory cells are arrayed, each of the memory cells storing therein a first logic state with a threshold voltage lower than or equal to a first value or a second logic state with a threshold voltage higher than or equal to a second value that is higher than the first value, a data hold circuit for holding program data and sensing data as read out of the memory cell array, and a controller configured to control a program sequence, wherein the controller has the control functions of: a program control function for applying a program voltage to a selected memory cell of the memory cell array to let the data shift from the first logic state to the second logic state; a program verify control function for verifying that the programmed data of the selected memory cell shifted to the second logic state; an erratic program verify control function for checking that the threshold voltage of a memory cell to be held in the first logic state does not exceed a third value set as an upper limit value of a variation of the first logic state; and an over-program verify control function for checking that the threshold voltage of the selected memory cell shifted to the second logic state does not exceed a fourth value set as an upper limit thereof.

摘要翻译： 一种非易失性半导体存储器件包括存储单元阵列，其中电可擦除可编程存储单元被排列，每个存储单元存储第一逻辑状态，阈值电压低于或等于第一值或第二逻辑 具有高于或等于高于第一值的第二值的阈值电压的状态，用于保存从存储单元阵列读出的程序数据和感测数据的数据保持电路，以及控制器，其被配置为控制程序序列 其中所述控制器具有以下控制功能：用于将程序电压施加到所述存储单元阵列的选定存储单元以使数据从第一逻辑状态移位到第二逻辑状态的程序控制功能; 程序验证控制功能，用于验证所选择的存储单元的编程数据移动到第二逻辑状态; 用于检查要保持在第一逻辑状态的存储单元的阈值电压不超过设置为第一逻辑状态的变化的上限值的第三值的不规则程序验证控制功能; 以及用于检查移动到第二逻辑状态的选择的存储单元的阈值电压不超过设定为其上限的第四值的过程序验证控制功能。

公开(公告)号：US07038946B2

公开(公告)日：2006-05-02

申请号：US11077046

申请日：2005-03-09

申请人： Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura

发明人： Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura

IPC分类号： G11C16/04

CPC分类号： G11C16/105 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/102 ,  G11C16/26 ,  G11C2216/14

摘要： A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address selector circuit for performing memory cell selection of the memory cell array, a data read/write circuit arranged to perform data read of the memory cell array and data write to the memory cell array, and a control circuit for executing a series of copy write operations in such a manner that a data output operation of from the data read/write circuit to outside of a chip and a data write operation of from the data read/write circuit to the memory cell array are overlapped each other, the copy write operation including reading data at a certain address of the memory cell array into the data read/write circuit, outputting read data held in the read/write circuit to outside of the chip and writing write data into another address of the memory cell array, the write data being a modified version of the read data held in the data read/write circuit as externally created outside the chip.

公开(公告)号：US06995410B2

公开(公告)日：2006-02-07

申请号：US10664538

申请日：2003-09-19

申请人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya

发明人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya

IPC分类号： H01L27/10

CPC分类号： G11C5/063 ,  G11C7/18 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L2924/0002 ,  H01L2924/00

摘要： Bit lines are arranged with minimum width and minimum space in a chip, and each bit line is given a maximum of first potential difference. The minimum space is the value which will not make a line short-circuit in a line due to dielectric strength, when the first potential difference is applied across the bit lines. This value may be the design rule or the minimum dimensions capable of being processed by lithography. A second potential difference lager than the first potential difference is applied across a shielded power line and the bit lines. The shielded power line is not adjacent to the bit lines in the wiring width direction in the area where the bit lines are arranged with the minimum space.

摘要翻译： 位线布置在芯片中具有最小宽度和最小空间，并且每个位线被给予最大的第一电位差。 最小空间是当第一电位差施加在位线上时由于介电强度而不会使线路短路的值。 该值可以是能够通过光刻处理的设计规则或最小尺寸。 在屏蔽电源线和位线之间施加比第一电位差较大的第二电位差。 屏蔽电源线在布线宽度方向上的位线不与最小间隔排列的区域相邻。

公开(公告)号：US20050185468A1

公开(公告)日：2005-08-25

申请号：US11117669

申请日：2005-04-28

申请人： Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Mikito Nakabayashi ,  Koichi Kawai

发明人： Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Mikito Nakabayashi ,  Koichi Kawai

IPC分类号： G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3463 ,  G11C16/3454 ,  G11C16/3459

摘要： A non-volatile semiconductor memory device includes a memory cell array in which electrically erasable and programmable memory cells are arrayed, each of the memory cells storing therein a first logic state with a threshold voltage lower than or equal to a first value or a second logic state with a threshold voltage higher than or equal to a second value that is higher than the first value, a data hold circuit for holding program data and sensing data as read out of the memory cell array, and a controller configured to control a program sequence, wherein the controller has the control functions of: a program control function for applying a program voltage to a selected memory cell of the memory cell array to let the data shift from the first logic state to the second logic state; a program verify control function for verifying that the programmed data of the selected memory cell shifted to the second logic state; an erratic program verify control function for checking that the threshold voltage of a memory cell to be held in the first logic state does not exceed a third value set as an upper limit value of a variation of the first logic state; and an over-program verify control function for checking that the threshold voltage of the selected memory cell shifted to the second logic state does not exceed a fourth value set as an upper limit thereof.

摘要翻译： 一种非易失性半导体存储器件包括存储单元阵列，其中电可擦除可编程存储单元被排列，每个存储单元存储第一逻辑状态，阈值电压低于或等于第一值或第二逻辑 具有高于或等于高于第一值的第二值的阈值电压的状态，用于保存从存储单元阵列读出的程序数据和感测数据的数据保持电路，以及控制器，其被配置为控制程序序列 其中所述控制器具有以下控制功能：用于将程序电压施加到所述存储单元阵列的选定存储单元以使数据从第一逻辑状态移位到第二逻辑状态的程序控制功能; 程序验证控制功能，用于验证所选择的存储单元的编程数据移动到第二逻辑状态; 用于检查要保持在第一逻辑状态的存储单元的阈值电压不超过设置为第一逻辑状态的变化的上限值的第三值的不规则程序验证控制功能; 以及用于检查移动到第二逻辑状态的选择的存储单元的阈值电压不超过设定为其上限的第四值的过程序验证控制功能。

公开(公告)号：US20050029051A1

公开(公告)日：2005-02-10

申请号：US10918686

申请日：2004-08-13

申请人： Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura

发明人： Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  F03G5/00

CPC分类号： G11C16/105 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/102 ,  G11C16/26 ,  G11C2216/14

摘要： A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address selector circuit for performing memory cell selection of the memory cell array, a data read/write circuit arranged to perform data read of the memory cell array and data write to the memory cell array, and a control circuit for executing a series of copy write operations in such a manner that a data output operation of from the data read/write circuit to outside of a chip and a data write operation of from the data read/write circuit to the memory cell array are overlapped each other, the copy write operation including reading data at a certain address of the memory cell array into the data read/write circuit, outputting read data held in the read/write circuit to outside of the chip and writing write data into another address of the memory cell array, the write data being a modified version of the read data held in the data read/write circuit as externally created outside the chip.

摘要翻译： 一种非易失性半导体存储器件包括其中布置有电可重写非易失性存储器单元的存储单元阵列，用于执行存储单元阵列的存储单元选择的地址选择器电路，布置成执行数据读取的数据读/写电路 的存储单元阵列和写入存储单元阵列的数据;以及控制电路，用于执行一系列复制写入操作，使得从数据读/写电路到芯片外部的数据输出操作和 从数据读/写电路到存储单元阵列的数据写入操作彼此重叠，复制写操作包括将存储单元阵列的特定地址处的数据读入数据读/写电路，输出保持在 读/写电路到芯片外部，并将写入数据写入存储单元阵列的另一个地址，写数据是保存在数据读/写中的读数据的修改版本 ite电路在芯片外部外部创建。