公开(公告)号：US20050190598A1

公开(公告)日：2005-09-01

申请号：US11120118

申请日：2005-05-02

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： G11C7/00 ,  G11C14/00 ,  H01L21/336 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11539

摘要： Methods of fabricating memory devices having non-volatile and volatile memory are provided. A substrate is provided, wherein the substrate has a non-volatile memory region and a volatile memory region. The non-volatile memory region has a storage device, such as a split-gate transistor, that is fabricated in substantially the same process steps as a storage capacitor of the volatile memory region. The reduction of process steps allow mixed memory to be fabricated in a cost effective manner.

公开(公告)号：US20050184331A1

公开(公告)日：2005-08-25

申请号：US10786798

申请日：2004-02-25

申请人： Kuo-Chi Tu ,  Wen-Ting Chu ,  Yi-Shing Chang ,  Yi-Jiun Lin

发明人： Kuo-Chi Tu ,  Wen-Ting Chu ,  Yi-Shing Chang ,  Yi-Jiun Lin

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers. A conductive control gate is disposed over the intergate insulator layer, covering about half of the floating gate.

摘要翻译： 公开了一种用于防止反向隧道的分裂门闪存单元结构。 在半导体表面上形成栅极绝缘体层，并且在栅极绝缘体层上方设置浮置栅极。 浮置栅极绝缘体层设置在浮置栅极之上，并且侧壁绝缘体间隔物沿邻近所述栅极绝缘体层的浮动栅极侧壁的底部设置。 侧壁绝缘体间隔物由间隔绝缘体层形成，该间隔绝缘体层以构成可用热预算的最小消耗量的方式沉积，并且蚀刻工艺用于形成侧壁绝缘体间隔层比栅极绝缘体层更快蚀刻间隔绝缘体层， 浮栅绝缘体层。 栅极绝缘体层设置在栅极绝缘体层，浮置栅极，浮置栅极绝缘体层和侧壁绝缘体间隔物的暴露部分之上。 导电控制栅极设置在栅极绝缘体层之上，覆盖浮动栅极的大约一半。

公开(公告)号：US20050093147A1

公开(公告)日：2005-05-05

申请号：US10696006

申请日：2003-10-29

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/48 ,  H01L27/108 ,  H01L29/40

CPC分类号： H01L27/10852 ,  H01L23/485 ,  H01L27/10811 ,  H01L27/10894 ,  H01L27/10897

摘要： A method for fabricating an insulating layer having contact openings of varying depths for logic/DRAM circuits is achieved using a single mask and etch step. After forming stacked or trench capacitors, a planar insulating layer is formed. Contact openings are etched in the planar insulating layer to the substrate, and contact openings that extend over the edge of the stacked or trench capacitor top electrode, having an ARC, are etched using a novel mask design and a single etching step. This allows one to make contacts to the substrate without overetching while making low-resistance contacts to the sidewall of the capacitor top electrode. In the trench capacitor open areas are formed to facilitate making contact openings that extend over the top electrode. A series of contact openings that are skewed or elongated also improve the latitude in alignment tolerance.

摘要翻译： 使用单个掩模和蚀刻步骤来实现用于制造具有用于逻辑/ DRAM电路的不同深度的接触开口的绝缘层的方法。 在形成堆叠或沟槽电容器之后，形成平面绝缘层。 接触开口在平面绝缘层中蚀刻到基板上，并且使用新颖的掩模设计和单个蚀刻步骤蚀刻在具有ARC的堆叠或沟槽电容器顶部电极的边缘上延伸的接触开口。 这允许在对电容器顶部电极的侧壁进行低电阻接触的同时，不过度地进行与基板的接触。 在沟槽电容器中形成开放区域以便于形成在顶部电极上延伸的接触开口。 歪斜或伸长的一系列接触开口也提高了对准公差的纬度。

公开(公告)号：US20050085038A1

公开(公告)日：2005-04-21

申请号：US10686106

申请日：2003-10-15

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： G11C7/00 ,  G11C14/00 ,  H01L21/336 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11539

摘要： Methods of fabricating memory devices having non-volatile and volatile memory are provided. A substrate is provided, wherein the substrate has a non-volatile memory region and a volatile memory region. The non-volatile memory region has a storage device, such as a split-gate transistor, that is fabricated in substantially the same process steps as a storage capacitor of the volatile memory region. The reduction of process steps allow mixed memory to be fabricated in a cost effective manner.

摘要翻译： 提供了制造具有非易失性和易失性存储器的存储器件的方法。 提供了一种衬底，其中衬底具有非易失性存储区和易失性存储区。 非易失性存储器区域具有以与易失性存储器区域的存储电容器基本相同的工艺步骤制造的存储器件，例如分离栅极晶体管。 工艺步骤的减少允许以成本有效的方式制造混合存储器。

公开(公告)号：US06853024B1

公开(公告)日：2005-02-08

申请号：US10679098

申请日：2003-10-03

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10888 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10897 ,  H01L28/91

摘要： A semiconductor device includes a group of capacitors and a trench. Each capacitor includes a first conductive material layer, a dielectric layer, and a second conductive material layer. The dielectric layer is located between the first and second conductive material layers. The first conductive material layer coats an inside surface of a cup-shaped opening formed in an insulating layer. The trench is formed in the insulating layer. The trench extends between and crosses each of the capacitors in the group. The dielectric layer and the second conductive material layer are formed over the first conductive material layer in the cup-shaped openings and over an inside surface of the trench. The second conductive material layer extends between the capacitors of the group via the trench. Also, the second conductive material layer forms top electrodes for the capacitors of the group.

公开(公告)号：US20050012132A1

公开(公告)日：2005-01-20

申请号：US10618793

申请日：2003-07-15

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L21/02 ,  H01L21/027 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/76

CPC分类号： H01L28/60 ,  H01L21/0276 ,  H01L27/10861 ,  H01L27/10891 ,  H01L27/11

摘要： A method for fabricating a capacitor with overlying transistor without stress-induced voids is described. A capacitor stack is provided overlying a substrate. A stress-balancing dielectric layer is deposited overlying the stack. An anti-reflective coating (ARC) layer is deposited overlying the stress-balancing layer. The stack is patterned to form the capacitors. Gate transistors are formed overlying the capacitors wherein the stress-balancing layer prevents formation of stress-induced voids during the thermal processes involved in forming the gate transistors.

摘要翻译： 描述了一种制造具有不具有应力诱发空隙的上覆晶体管的电容器的方法。 覆盖在基板上的电容器叠层被提供。 叠层堆叠应力平衡介电层。 沉积在应力平衡层上的抗反射涂层（ARC）层。 图案化堆叠以形成电容器。 形成覆盖电容器的栅极晶体管，其中应力平衡层在形成栅极晶体管的热处理期间阻止形成应力诱导的空隙。

公开(公告)号：US06294426B1

公开(公告)日：2001-09-25

申请号：US09765041

申请日：2001-01-19

申请人： Kuo-Chi Tu ,  Chih-Hsing Yu

发明人： Kuo-Chi Tu ,  Chih-Hsing Yu

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L27/10811 ,  H01L27/10855 ,  H01L28/84 ,  H01L28/90 ,  Y10S438/964

摘要： A process for fabricating a capacitor under bit line (CUM), DRAM device, featuring increased capacitance, without increasing the aspect ratio for a dry etched, narrow diameter bit line contact hole, has been developed. The process features increasing the vertical space in a capacitor opening, needed to accommodate a capacitor structure with increased vertical dimensions, via selective removal of the top portions of the polysilicon plug structures exposed in the capacitor openings. The depth of a subsequent bit line contact hole, opened to a non-truncated polysilicon plug structure, is therefore not increased as a result of the increase capacitor depth, thus not resulting in an increased aspect ratio for the dry etched, narrow diameter bit line contact hole.

摘要翻译： 已经开发了用于在位线（CUM）下制造电容器的过程，具有增加的电容的DRAM器件，而不增加用于干蚀刻的窄直径位线接触孔的纵横比。 该方法特征在于，通过选择性地去除暴露在电容器开口中的多晶硅插塞结构的顶部部分，增加电容器开口中垂直空间，以容纳具有增加的垂直尺寸的电容器结构。 因此，由于增加了电容器的深度，所以随后的位线接触孔的深度开放到非截短多晶硅插塞结构，因此不会增加干蚀刻的窄直径位线的纵横比 接触孔。

公开(公告)号：US08617949B2

公开(公告)日：2013-12-31

申请号：US13267424

申请日：2011-10-06

申请人： Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chen-Jong Wang

发明人： Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chen-Jong Wang

IPC分类号： H01L21/8242

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system-on-chip device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, and so forth.

摘要翻译： 片上系统装置包括第一区域中的第一电容器，第二区域中的第二电容器，并且还可以包括第三区域中的第三电容器，以及附加区域中的任何附加数量的电容器。 电容器可以具有不同的形状和尺寸。 区域可以包括多于一个的电容器。 区域中的每个电容器具有顶部电极，底部电极和电容器绝缘体。 所有电容器的顶部电极以公共工艺形成，而所有电容器的底部电极形成在共同的工艺中。 电容器绝缘体可以具有不同数量的亚层，形成不同的材料或厚度。 电容器可以形成在层间电介质层中或在金属间介电层中。 这些区域可以是混合信号区域，模拟区域等。

公开(公告)号：US08143699B2

公开(公告)日：2012-03-27

申请号：US12618021

申请日：2009-11-13

申请人： Kuo-Cheng Ching ,  Kuo-Chi Tu

发明人： Kuo-Cheng Ching ,  Kuo-Chi Tu

IPC分类号： H01L29/92

CPC分类号： H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a chip having a first region and a second region. A first metal-insulator-metal (MIM) capacitor is formed in the first region. The first MIM capacitor has a first bottom electrode; a first top electrode over the first bottom electrode; and a first capacitor insulator between and adjoining the first bottom electrode and the first top electrode. A second MIM capacitor is in the second region and is substantially level with the first MIM capacitor. The second MIM capacitor includes a second bottom electrode; a second top electrode over the second bottom electrode; and a second capacitor insulator between and adjoining the second bottom electrode and the second top electrode. The second capacitor insulator is different from the first capacitor insulator. The first top electrode and the first bottom electrode may be formed simultaneously with the second top electrode and the second bottom electrode, respectively.

摘要翻译： 集成电路结构包括具有第一区域和第二区域的芯片。 在第一区域形成第一金属绝缘体金属（MIM）电容器。 第一MIM电容器具有第一底部电极; 位于所述第一底部电极之上的第一顶部电极; 以及在所述第一底部电极和所述第一顶部电极之间并邻接所述第一电极绝缘体。 第二MIM电容器在第二区域中，并且与第一MIM电容器基本一致。 第二MIM电容器包括第二底部电极; 在所述第二底部电极上方的第二顶部电极; 以及在所述第二底部电极和所述第二顶部电极之间并邻接所述第二电极绝缘体。 第二电容绝缘体与第一电容绝缘体不同。 第一顶部电极和第一底部电极可以分别与第二顶部电极和第二底部电极同时形成。

公开(公告)号：US07745865B2

公开(公告)日：2010-06-29

申请号：US11184786

申请日：2005-07-20

申请人： Kuo-Chi Tu

发明人： Kuo-Chi Tu

IPC分类号： H01L27/108

CPC分类号： H01L28/60 ,  H01L27/10855

摘要： Devices and methods for preventing capacitor leakage caused by sharp tip. The formation of sharp tip is avoided by a thicker bottom electrode which fully fills a micro-trench that induces formation of the sharp tip. Alternatively, formation of the sharp tip can be avoided by recessing the contact plug to substantially eliminate the micro-trench.

摘要翻译： 用于防止由尖端引起的电容器泄漏的装置和方法。 通过较厚的底部电极避免形成尖锐尖端，该底部电极完全填充引起锋利尖端形成的微沟槽。 或者，可以通过使接触插塞凹陷以基本上消除微沟槽来避免尖端尖端的形成。