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61.发明授权Physical interface macros (PHYS) supporting heterogeneous electrical properties 失效物理接口宏（PHYS）支持异质电气特性公开(公告)号：US08051228B2
公开(公告)日：2011-11-01
申请号：US12270576
申请日：2008-11-13
CPC分类号： G06F13/4022 , G06F13/4072 , G06F2213/0026 , G06F2213/0028 , Y02D10/14 , Y02D10/151
摘要： An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage.
摘要翻译： 集成处理器设计包括支持异质电气特性的物理接口宏。 处理器设计包括多个处理核心和多个物理接口以连接到存储器接口，用于输入/输出的外围组件互连快速（PCI Express或PCIe）接口，用于网络通信的以太网接口和/或 串行连接SCSI（SAS）接口进行存储。
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公开(公告)号：US20110173630A1
公开(公告)日：2011-07-14
申请号：US12024384
申请日：2008-02-01
IPC分类号： G06F9/48
摘要： A wake-and-go mechanism is provided with a central repository wake-and-go array for a multiple processor data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread running on a processor within the multiple processor data processing system is waiting for an event. The wake-and-go mechanism updates a central repository wake-and-go array with a target address associated with the event. Each entry in the central repository wake-and-go array may include a thread identification (ID), a central processing unit (CPU) ID, the target address, the expected data, a comparison type, a lock bit, a priority, and a thread state pointer, which is the address at which the thread state information is stored.
摘要翻译： 提供了一个唤醒机制，具有用于多处理器数据处理系统的中央存储库唤醒阵列。 唤醒机制识别一种编程习语，其指示在多处理器数据处理系统中的处理器上运行的线程正在等待事件。 唤醒机制更新了具有与事件相关联的目标地址的中央存储库唤醒数组。 中央存储库唤醒阵列中的每个条目可以包括线程标识（ID），中央处理单元（CPU）ID，目标地址，预期数据，比较类型，锁定位，优先级和 线程状态指针，其是存储线程状态信息的地址。
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公开(公告)号：US20110173419A1
公开(公告)日：2011-07-14
申请号：US12024419
申请日：2008-02-01
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3806
摘要： A wake-and-go mechanism is provided for a microprocessor. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms that indicates that the thread is waiting for an event. If a look-ahead polling operation succeeds, the look-ahead wake-and-go engine may record an instruction address for the corresponding idiom so that the wake-and-go mechanism may have the thread perform speculative execution at a time when the thread is waiting for an event. During execution, when the wake-and-go mechanism recognizes a programming idiom, the wake-and-go mechanism may store the thread state in the thread state storage. Instead of putting thread to sleep, the wake-and-go mechanism may perform speculative execution.
摘要翻译： 为微处理器提供唤醒机制。 唤醒机制在针对线程正在等待事件的编程习语的线程的指令流中向前看。 如果先行轮询操作成功，先行后唤醒引擎可以记录相应成语的指令地址，使得唤醒机制可能使线程在线程执行推测执行时 正在等待一个事件。 在执行期间，当唤醒机制识别出编程习惯时，唤醒机制可以将线程状态存储在线程状态存储器中。 唤醒机制可能会执行推测性的执行，而不是让线程睡眠。
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64.发明授权公开(公告)号：US07958182B2
公开(公告)日：2011-06-07
申请号：US11845223
申请日：2007-08-27
IPC分类号： G06F15/16
CPC分类号： G06F15/17381
摘要： A mechanism is provided for performing collective operations. In hardware of a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In hardware of the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output.
摘要翻译： 提供了一种用于执行集体操作的机制。 在第一处理器书中的母处理器的硬件中，在执行集体操作所需的数据处理系统的相同或不同的处理器簿中确定多个其他处理器，由此建立多个处理器，其包括母处理器 和其他处理器。 在母处理器的硬件中，多个处理器在逻辑上被布置为分层结构中的多个节点。 基于层次结构将集体操作发送到多个处理器。 在母处理器的硬件中，从其他处理器的集体操作的执行中接收到结果，基于接收到的结果生成集合操作的最终结果，并输出最终结果。
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公开(公告)号：US07937570B2
公开(公告)日：2011-05-03
申请号：US12024546
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/3834 , G06F9/3885
摘要： A data processing system has a processor, a memory, and an instruction set architecture (ISA) that includes: an asynchronous memory mover (AMM) store (ST) instruction that initiates an asynchronous memory move operation that moves data from a first memory location having a first real address to a second memory location having a second real address by: (a) first performing a move of the data in virtual address space utilizing a source effective address a destination effective address; and (b) when the move is completed, completing a physical move of the data to the second memory location, independent of the processor. The ISA further provides an AMM terminate ST instruction for stopping an ongoing AMM operation before completion of the AMM operation, and a LD CMP instruction for checking a status of an AMM operation.
摘要翻译： 数据处理系统具有处理器，存储器和指令集架构（ISA），其包括：异步存储器移动器（AMM）存储（ST）指令，其启动异步存储器移动操作，其从具有第一存储器位置的第一存储器位置移动数据， 具有第二实际地址的第二存储器位置的第一实际地址：（a）首先使用源有效地址执行虚拟地址空间中的数据移动目的地有效地址; 和（b）当移动完成时，完成数据到第二存储器位置的物理移动，而与处理器无关。 ISA还提供用于在完成AMM操作之前停止正在进行的AMM操作的AMM终止ST指令，以及用于检查AMM操作的状态的LD CMP指令。
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66.发明授权Full virtualization of resources across an IP interconnect using page frame table 失效使用页面框架表在IP互连中完全虚拟化资源公开(公告)号：US07904693B2
公开(公告)日：2011-03-08
申请号：US12024773
申请日：2008-02-01
IPC分类号： G06F12/10
CPC分类号： G06F12/10 , G06F12/1081 , H04L29/12018 , H04L61/10
摘要： An addressing model is provided where devices, including I/O devices, are addressed with internet protocol (IP) addresses, which are considered part of the virtual address space. A task, such as an application, may be assigned an effective address range, which corresponds to addresses in the virtual address space. The virtual address space is expanded to include Internet protocol addresses. Thus, the page frame tables are also modified to include entries for IP addresses and additional properties for devices and I/O. Thus, a processing element, such as an I/O adapter or even a printer, for example, may also be addressed using IP addresses without the need for library calls, device drivers, pinning memory, and so forth. This addressing model also provides full virtualization of resources across an IP interconnect, allowing a process to access an I/O device across a network.
摘要翻译： 提供了一种寻址模型，其中包括I / O设备在内的设备通过互联网协议（IP）地址进行寻址，这些地址被认为是虚拟地址空间的一部分。 可以为任务（例如应用程序）分配与虚拟地址空间中的地址对应的有效地址范围。 虚拟地址空间被扩展为包括互联网协议地址。 因此，页框表也被修改为包括用于设备和I / O的IP地址和附加属性的条目。 因此，例如，诸如I / O适配器或甚至打印机的处理元件也可以使用IP地址来寻址，而不需要库调用，设备驱动器，固定存储器等。 该寻址模型还可以跨IP互连提供资源的完全虚拟化，从而允许进程通过网络访问I / O设备。
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67.发明授权公开(公告)号：US07904590B2
公开(公告)日：2011-03-08
申请号：US11845215
申请日：2007-08-27
IPC分类号： G06F15/173
CPC分类号： G06F15/17381
摘要： A mechanism is provided for routing information through the data processing system. Data is received at a source processor within a set of processors that is to be transmitted to a destination processor, where the data includes address information. A first determination is performed as to whether the destination processor is within a same processor book as the source processor based on the address information. A second determination is performed as to whether the destination processor is within a same supernode as the source processor based on the address information if the destination processor is not within the same processor book. A routing path is identified for the data based on results of the first determination, the second determination, and one or more routing table data structures. The data is then transmitted from the source processor along the identified routing path toward the destination processor.
摘要翻译： 提供了一种通过数据处理系统路由信息的机制。 在要发送到目标处理器的一组处理器内的源处理器处接收数据，其中数据包括地址信息。 基于地址信息，执行目的地处理器是否在与处理器相同的处理器簿内的第一确定。 如果目的地处理器不在相同的处理器书中，则基于地址信息来执行关于目的地处理器是否在与源处理器相同的超级节点内的第二确定。 基于第一确定，第二确定和一个或多个路由表数据结构的结果，为数据识别路由路径。 然后将数据从源处理器沿着识别的路由路径发送到目的地处理器。
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公开(公告)号：US07895374B2
公开(公告)日：2011-02-22
申请号：US12165809
申请日：2008-07-01
CPC分类号： G06F13/4243 , G06F11/2007 , G06F11/2017 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译： 用于在存储器系统中提供动态段保存和修复的通信接口设备，系统，方法和设计结构。 通信接口装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。 该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段 。
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公开(公告)号：US07890703B2
公开(公告)日：2011-02-15
申请号：US12359565
申请日：2009-01-26
申请人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
CPC分类号： G06F9/30032 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F12/0862 , G06F12/0888 , G06F12/0897 , G06F2212/6028
摘要： A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a start of a semi-synchronous memory copy operation. The semi-synchronous memory copy operation is checked for a given value in at least one cache injection bit. In response to the given value in the cache injection bit, a predefined number of lines of destination data is copied into at least one level of cache memory.
摘要翻译： 公开了一种基于半同步存储器复制指令中的信息将数据插入高速缓冲存储器的系统，方法和计算机。 该方法包括确定半同步存储器复制操作的开始。 在至少一个高速缓存注入位中检查给定值的半同步存储器复制操作。 响应于高速缓存注入位中的给定值，预定数量的目的地数据行被复制到至少一级的高速缓存存储器中。
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70.发明授权Validity of address ranges used in semi-synchronous memory copy operations 有权在半同步存储器复制操作中使用的地址范围的有效性公开(公告)号：US07882321B2
公开(公告)日：2011-02-01
申请号：US12402904
申请日：2009-03-12
申请人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
IPC分类号： G06F12/02
CPC分类号： G06F12/1441 , G06F12/0888 , G06F12/0897
摘要： A system, method, and a computer readable for protecting content of a memory page are disclosed. The method includes determining a start of a semi-synchronous memory copy operation. A range of addresses is determined where the semi-synchronous memory copy operation is being performed. An issued instruction that removes a page table entry is detected. The method further includes determining whether the issued instruction is destined to remove a page table entry associated with at least one address in the range of addresses. In response to the issued instruction being destined to remove the page table entry, the execution of the issued instruction is stalled until the semi-synchronous memory copy operation is completed.
摘要翻译： 公开了一种用于保护存储器页面的内容的系统，方法和可读取的计算机。 该方法包括确定半同步存储器复制操作的开始。 确定正在执行半同步存储器复制操作的地址范围。 检测到发出的删除页表条目的指令。 所述方法还包括确定所发出的指令是否旨在去除与地址范围中的至少一个地址相关联的页表条目。 响应于发出的指令旨在去除页表条目，所发出的指令的执行停止，直到半同步存储器复制操作完成。
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