公开(公告)号：US20190140172A1

公开(公告)日：2019-05-09

申请号：US15805209

申请日：2017-11-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Dai-Ying Lee ,  Po-Hao Tseng ,  Feng-Min Lee ,  Yu-Yu Lin ,  Kai-Chieh Hsu

IPC: H01L45/00 ,  H01L27/24

Abstract: A contact hole structure includes a substrate, an interlayer dielectric (ILD), a conductive layer and an insulating capping layer. The ILD is disposed on the substrate and has a first opening. The conductive layer is disposed in the ILD and aligns the first opening. The insulating capping layer has a spacer disposed on a first sidewall of the first opening, wherein the spacer contacts to the conductive layer and defines a second opening in the first opening, so as to expose a portion of the conductive layer.

公开(公告)号：US10242737B1

公开(公告)日：2019-03-26

申请号：US15895369

申请日：2018-02-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee

IPC: G11C13/00 ,  H01L27/24 ,  G06N3/063 ,  H01L45/00

Abstract: An array of resistance cells has a number M of rows and a number N of columns of resistance cells. Each cell comprises a transistor having a threshold, representing a weight factor Wnm of the cell, and a resistive element in series with the transistor. Each cell has a cell resistance having a first value when the transistor is on and a second value when the transistor is off. A set of source lines is coupled to the resistance cells in respective columns. A set of bit lines is coupled to the resistance cells in respective rows, signals on the bit lines representing inputs x(m) to the respective rows. A set of word lines is coupled to gates of the transistors in the resistance cells in respective columns. Current sensed at a particular source line represents a sum of products of the inputs x(m) by respective weight factors Wnm.

公开(公告)号：US10115769B1

公开(公告)日：2018-10-30

申请号：US15620880

申请日：2017-06-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Feng-Min Lee ,  Yu-Yu Lin ,  Kai-Chieh Hsu

IPC: H01L27/24 ,  H01L45/00

Abstract: A ReRAM device is provided. The ReRAM device comprises a first dielectric layer disposed on a substrate and covering a gate oxide structure on the substrate, a first conductive connecting structure disposed on the substrate and penetrating the first dielectric layer, and a ReRAM unit disposed on the first conductive connecting structure. The first dielectric layer comprises a first insulating layer disposed on the substrate, and a stop layer disposed on the first insulating layer and contacting a top surface of the gate oxide structure, wherein the stop layer is a hydrogen controlled layer.

公开(公告)号：US09947403B1

公开(公告)日：2018-04-17

申请号：US15469672

申请日：2017-03-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Kai-Chieh Hsu

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0073 ,  G11C2013/0092

Abstract: A method for operating a resistance switching memory device is provided, wherein the method includes a first program process, and the first program process includes steps as follows: A programming pulse having a first polarity is firstly applied to at least one resistance switching memory cell of the NVM device. A first verifying pulse with a verifying voltage is then applied to the resistance switching memory cell. A first settling pulse is applied to the resistance switching memory cell prior to or after the verifying pulse is applied, wherein the first settling pulse includes a settling voltage having a second polarity opposite to the first polarity and an absolute value substantially less than that of the verifying voltage.

公开(公告)号：US09947398B1

公开(公告)日：2018-04-17

申请号：US15482978

申请日：2017-04-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan Lin ,  Kai-Chieh Hsu ,  Yu-Yu Lin ,  Feng-Min Lee

IPC: G11C11/00 ,  G11C13/00 ,  G06F1/32

CPC classification number: G11C13/0038 ,  G11C13/004 ,  G11C2013/0054

Abstract: A semiconductor memory device includes: a memory array including a plurality of memory cells, the memory cells being in any of a high resistance state (HRS) and a low resistance state (LRS); a reference array including a plurality of reference cells, the memory cells and the reference cells having the same impedance-temperature relationship, the reference cells being in a middle resistance state between HRS and LRS; an average circuit configured for averaging respective reference currents from the reference cells of the reference array into an average reference current; and a comparator configured for comparing a plurality of respective memory currents from the memory cells of the memory array with the average reference current to obtain a plurality of output data of the memory cells of the memory array and to determine respective impedance states of the memory cells of the memory array.

公开(公告)号：US09583700B2

公开(公告)日：2017-02-28

申请号：US14746703

申请日：2015-06-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Feng-Min Lee ,  Yu-Yu Lin ,  Dai-Ying Lee

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

Abstract: The present invention relates to metal oxide based memory devices and methods for manufacturing such devices; and more particularly to memory devices having data storage materials based on metal oxide compounds fabricated with a roughness tuning process including an ion bombardment step of a bottom electrode surface prior to formation of a memory element on the bottom electrode surface. Ion bombardment improves the flatness of the bottom electrode which is beneficial in achieving a more uniform electrical field during operation, which improves device reliability.

Abstract translation: 本发明涉及基于金属氧化物的记忆装置及其制造方法。 并且更具体地涉及具有基于金属氧化物化合物的数据存储材料的存储器件，所述金属氧化物化合物在粗糙度调整过程包括在底部电极表面上形成存储元件之前包括底部电极表面的离子轰击步骤制造。 离子轰击改善了底部电极的平坦度，这有利于在操作期间实现更均匀的电场，这提高了器件的可靠性。

公开(公告)号：US20160218284A1

公开(公告)日：2016-07-28

申请号：US14729181

申请日：2015-06-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Chien-Hung Lu ,  Chin-Yi Tseng

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1633 ,  H01L45/1683

Abstract: A memory structure including an insulating layer, a first electrode layer and a first barrier is provided. The insulating layer has a recess. The first electrode layer is formed in the recess and has a first top surface. The first barrier is formed between the insulating layer and the first electrode layer, and has a second top surface lower than the first top surface. The first top surface and the second top surface are lower than an opening of the recess.

Abstract translation: 提供了包括绝缘层，第一电极层和第一屏障的存储结构。 绝缘层具有凹部。 第一电极层形成在凹部中并且具有第一顶表面。 第一阻挡层形成在绝缘层和第一电极层之间，并且具有比第一顶表面低的第二顶表面。 第一顶表面和第二顶表面比凹口的开口低。

公开(公告)号：US09196361B2

公开(公告)日：2015-11-24

申请号：US14085839

申请日：2013-11-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ming-Hsiu Lee ,  Feng-Min Lee ,  Yu-Yu Lin

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/79

Abstract: Provided is an operation method applicable to a resistive memory cell including a transistor and a resistive memory element. The operation method includes: in a programming operation, generating a programming current flowing through the transistor and the resistive memory element so that a resistance state of the resistive memory element changes from a first resistance state into a second resistance state; and in an erase operation, generating an erase current from a well region of the transistor to the resistive memory element but keeping the erase current from flowing through the transistor, so that the resistance state of the resistive memory element changes from the second resistance state into the first resistance state.

Abstract translation: 提供了一种适用于包括晶体管和电阻性存储元件的电阻式存储单元的操作方法。 操作方法包括：在编程操作中，产生流过晶体管和电阻存储元件的编程电流，使得电阻性存储元件的电阻状态从第一电阻状态变为第二电阻状态; 并且在擦除操作中，产生从晶体管的阱区到电阻存储元件的擦除电流，但是保持擦除电流不流过晶体管，使得电阻性存储元件的电阻状态从第二电阻状态变为 第一个阻力状态。

公开(公告)号：US09190612B1

公开(公告)日：2015-11-17

申请号：US14297689

申请日：2014-06-06

Applicant: Macronix International Co., Ltd.

Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC: H01L23/52 ,  H01L45/00

CPC classification number: H01L45/1233 ,  G11C13/0007 ,  H01L45/04 ,  H01L45/08 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1633

Abstract: A semiconductor structure, a resistive random access memory unit structure, and a manufacturing method of the semiconductor structure are provided. The semiconductor structure includes an insulating structure, a stop layer, a metal oxide layer, a resistance structure, and an electrode material layer. The insulating structure has a via, and the stop layer is formed in the via. The metal oxide layer is formed on the stop layer. The resistance structure is formed at a bottom of an outer wall of the metal oxide layer. The electrode material layer is formed on the metal oxide layer.

Abstract translation: 提供半导体结构，电阻随机存取存储器单元结构以及半导体结构的制造方法。 半导体结构包括绝缘结构，停止层，金属氧化物层，电阻结构和电极材料层。 绝缘结构具有通孔，并且阻挡层形成在通路中。 在停止层上形成金属氧化物层。 电阻结构形成在金属氧化物层的外壁的底部。 在金属氧化物层上形成电极材料层。

公开(公告)号：US12277968B2

公开(公告)日：2025-04-15

申请号：US18330369

申请日：2023-06-07

Applicant: MACRONIX International Co., Ltd.

Inventor： Yu-Yu Lin ,  Feng-Min Lee

IPC: G11C13/00

Abstract: An in-memory computation device includes multiple computation blocks, a first reference weight block, and an output result generator. The computation blocks have multiple weighting values, receive multiple input signals respectively, and generate multiple computation results. Each of the computation blocks generates each of the computation results according to each of the corresponding input signals and corresponding weighting values. The first reference weight block provides a first reference resistance according to multiple reference weighting values and generates a first reference signal according to the first reference resistance and a read voltage. The output result generator generates multiple output computation results according to the first reference signal and the computation results.