公开(公告)号：US20080163331A1

公开(公告)日：2008-07-03

申请号：US11618649

申请日：2006-12-29

申请人： Sham M. Datta ,  Mohan J. Kumar ,  James A. Sutton ,  Ernie Brickell ,  Ioannis T. Schoinas

发明人： Sham M. Datta ,  Mohan J. Kumar ,  James A. Sutton ,  Ernie Brickell ,  Ioannis T. Schoinas

IPC分类号： G06F21/00 ,  G06F17/00

CPC分类号： G06F21/57

摘要： Apparatuses, methods, and systems for reconfiguring a secure system are disclosed. In one embodiment, an apparatus includes a configuration storage location, a lock, and lock override logic. The configuration storage location is to store information to configure the apparatus. The lock is to prevent writes to the configuration storage location. The lock override logic is to allow instructions executed from sub-operating mode code to override the lock.

摘要翻译： 公开了用于重新配置安全系统的装置，方法和系统。 在一个实施例中，装置包括配置存储位置，锁定和锁定超驰逻辑。 配置存储位置是存储信息以配置设备。 该锁是为了防止写入配置存储位置。 锁定覆盖逻辑是允许从子操作模式代码执行的指令覆盖锁定。

公开(公告)号：US6065123A

公开(公告)日：2000-05-16

申请号：US978545

申请日：1997-11-26

申请人： Stephen T. Chou ,  Russell J. Fenger ,  Mohan J. Kumar ,  Victor B. Lortz ,  Benjamin L. Manny ,  Mil Travnicek ,  Chih-Kan Wang

发明人： Stephen T. Chou ,  Russell J. Fenger ,  Mohan J. Kumar ,  Victor B. Lortz ,  Benjamin L. Manny ,  Mil Travnicek ,  Chih-Kan Wang

IPC分类号： G06F1/32 ,  G06F11/14 ,  G06F9/00

CPC分类号： G06F1/3265 ,  G06F1/3203 ,  G06F1/3209 ,  G06F11/1441 ,  Y02B60/1242

摘要： A computer system with unattended on-demand availability includes power-saving features which place the system into a Standby mode whenever the system is idle or is not being used. Prior to entering Standby mode, the system sets a hardware timer which indicates when the next scheduled event in the system should be performed. When either the timer expires or another event occurs which requires system operation, the system resumes to the On power state without user intervention. In one embodiment, the system of the present invention allows applications to periodically save their operational states. By saving their operational states, applications are able to guard against power failures and crashes. If a power failure or crash occurs, the system consults restart policies and, if appropriate, automatically re-starts applications to their most recently saved operational states once power is re-stored.

摘要翻译： 具有无人值守按需可用性的计算机系统包括省电功能，当系统空闲或未使用时，系统进入待机模式。 在进入待机模式之前，系统设置一个硬件定时器，指示系统中下次调度的事件何时执行。 当定时器超时或需要系统操作的另一个事件时，系统将恢复到On电源状态，无需用户干预。 在一个实施例中，本发明的系统允许应用程序周期性地保存其操作状态。 通过保存操作状态，应用程序能够防止电源故障和崩溃。 如果发生电源故障或发生故障，系统将重新启动策略，并在适当的情况下自动将应用程序重新启动到其最近保存的操作状态，一旦重新存储电源。

公开(公告)号：US5902352A

公开(公告)日：1999-05-11

申请号：US909384

申请日：1997-08-11

申请人： Stephen T. Chou ,  Russell J. Fenger ,  Mohan J. Kumar ,  Victor B. Lortz ,  Mil Travnicek ,  Chih-Kan Wang

发明人： Stephen T. Chou ,  Russell J. Fenger ,  Mohan J. Kumar ,  Victor B. Lortz ,  Mil Travnicek ,  Chih-Kan Wang

IPC分类号： G06F9/48 ,  G06F9/00

CPC分类号： G06F9/4881

摘要： A method and apparatus for task scheduling across multiple execution sessions allows each scheduled task to be scheduled to occur at a specific time(s), to occur periodically, or to occur in response to certain system events. A task can be scheduled which requires execution of an application even if the application is not running at the scheduled time or event, and even if the system is in a low-power standby mode at the scheduled time or event. In one embodiment, the present invention keeps track of specific time events by setting a timer(s) which indicates the time which should elapse until a scheduled event is to occur. When a timer expires, the system determines which task is scheduled to occur at the time the timer expires and executes that task. In one embodiment, the present invention checks a scheduling database to determine which task is scheduled to occur when a timer expires.

摘要翻译： 用于跨越多个执行会话的任务调度的方法和装置允许调度每个调度的任务在特定时间发生，周期性地发生，或者响应于某些系统事件而发生。 即使应用程序未在预定的时间或事件中运行，并且即使系统在预定时间或事件中处于低功耗待机模式，也可以调度任务，该任务需要执行应用程序。 在一个实施例中，本发明通过设置指示应该经过的时间的定时器来跟踪特定的时间事件，直到发生调度的事件。 当定时器到期时，系统确定在定时器到期时调度哪个任务发生，并执行该任务。 在一个实施例中，本发明检查调度数据库以确定当定时器到期时调度哪个任务发生。

公开(公告)号：US10331614B2

公开(公告)日：2019-06-25

申请号：US15025988

申请日：2013-11-27

申请人： INTEL CORPORATION ,  Dimitrios Ziakas ,  Bassam N. Coury ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Thi Dang ,  Russell J. Wunderlich

发明人： Dimitrios Ziakas ,  Bassam N. Coury ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Thi Dang ,  Russell J. Wunderlich

IPC分类号： G06F11/00 ,  G06F15/78 ,  G06F11/10 ,  G06F11/34 ,  G06F11/16

摘要： Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.

公开(公告)号：US20180034909A1

公开(公告)日：2018-02-01

申请号：US15221707

申请日：2016-07-28

申请人： Murugasamy K. Nachimuthu ,  Mohan J. Kumar

发明人： Murugasamy K. Nachimuthu ,  Mohan J. Kumar

IPC分类号： H04L29/08 ,  H04L12/24

摘要： Mechanisms for efficient discovery of storage resources in a Rack Scale Architecture (RSA) system and associated methods, apparatus, and systems. A rack is populated with pooled system drawers including pooled compute drawers and pooled storage drawers communicatively coupled via input-output (IO) cables. Compute nodes including one or more processors, memory resources, and optional local storage resources are installed in the pooled compute drawers, and are enabled to be selectively-coupled to storage resources in the pooled storage drawers over virtual attachment links. During a discovery process, a compute node determines storage resource characteristics of storage resources it may be selectively-coupled to and the attachment links used to access the storage resources. The storage resource characteristics are aggregated by a pod manager that uses corresponding configuration information to dynamically compose compute nodes for rack users based on user needs.

公开(公告)号：US09600416B2

公开(公告)日：2017-03-21

申请号：US13997189

申请日：2011-09-30

申请人： Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

发明人： Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

IPC分类号： G06F13/12 ,  G06F13/38 ,  G06F12/08 ,  G11C11/406 ,  G11C14/00

CPC分类号： G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/2024 ,  G06F2212/205 ,  G11C11/40615 ,  G11C14/009 ,  Y02D10/13

摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US09411667B2

公开(公告)日：2016-08-09

申请号：US13997870

申请日：2012-06-06

申请人： Sarathy Jayakumar ,  Mohan J. Kumar ,  Jose A. Vargas

发明人： Sarathy Jayakumar ,  Mohan J. Kumar ,  Jose A. Vargas

IPC分类号： G06F11/00 ,  G06F11/07

CPC分类号： G06F11/0751 ,  G06F11/0712 ,  G06F11/0745 ,  G06F11/0793

摘要： Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor.

摘要翻译： 本文描述了具有平台实体的计算设备，例如中断处理器的设备，计算机实现的方法，系统，设备和计算机可读介质的实施例，其被配置为通知在计算设备上执行的操作系统或虚拟机监视器 输入/输出错误容纳事件。 在各种实施例中，响应于来自操作系统或虚拟机监视器的指示，中断处理程序可以被配置为便于恢复导致输入/输出错误容纳事件的输入/输出设备的链接。

公开(公告)号：US09317360B2

公开(公告)日：2016-04-19

申请号：US13995458

申请日：2011-12-29

申请人： Jose A. Vargas ,  Mohan J. Kumar ,  James B. Crossland ,  Murugasamy K. Nachimuthu ,  Theodros Yigzaw

发明人： Jose A. Vargas ,  Mohan J. Kumar ,  James B. Crossland ,  Murugasamy K. Nachimuthu ,  Theodros Yigzaw

IPC分类号： G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F11/10 ,  G06F11/07

CPC分类号： G06F11/1004 ,  G06F11/0724 ,  G06F11/0793

摘要： In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.

摘要翻译： 在一些实现中，处理器可以包括具有多个错误报告寄存器的机器检查架构，其能够接收用于机器检查错误的数据。 总结寄存器可以包括多个可设置位置，每个位置可以代表错误报告寄存器中的至少一个。 可以将汇总寄存器中的一个或多个可设置位置设置为指示一个或多个错误报告寄存器是否保持机器检查错误的数据。 因此，当发生机器检查错误时，可以访问总结寄存器以识别处理器视图中的任何错误报告寄存器是否包含有效的错误数据，而不是在处理器视图中读取每个错误报告寄存器。

公开(公告)号：US09311138B2

公开(公告)日：2016-04-12

申请号：US13799327

申请日：2013-03-13

申请人： Sarathy Jayakumar ,  Mohan J. Kumar ,  Michael D. Kinney

发明人： Sarathy Jayakumar ,  Mohan J. Kumar ,  Michael D. Kinney

IPC分类号： G06F9/48 ,  G06F11/07

CPC分类号： G06F9/4812 ,  G06F11/0772

摘要： Technologies for system management interrupt (“SMI”) handling include a number of processor cores configured to enter a system management mode (“SMM”) in response to detecting an SMI. The first processor core to enter SMM and acquire a master thread lock sets an in-progress flag and executes a master SMI handler without waiting for other processor cores to enter SMM. Other processor cores execute a subordinate SMI handler. The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs. The multi-core processor may set an SMI service pending flag in response to detecting the SMI, which is cleared by the processor core that acquires the master thread lock. A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs. Other embodiments are described and claimed.

摘要翻译： 用于系统管理中断（“SMI”）处理的技术包括配置为响应于检测到SMI而进入系统管理模式（“SMM”）的多个处理器核心。 进入SMM并获取主线程锁的第一个处理器核心设置正在进行的标志，并执行主SMI处理程序，而不必等待其他处理器内核进入SMM。 其他处理器核心执行从属SMI处理程序。 主SMI处理程序可以指示下级SMI处理程序来处理核心特定的SMI。 响应于检测到由获取主线程锁的处理器核心清除的SMI，多核处理器可以设置SMI服务挂起标志。 进入SMM的处理器核心在确定进行中标志未被设置并且未设置服务暂挂标志时，可以立即恢复正常执行，以检测和减轻假SMI。 描述和要求保护其他实施例。

公开(公告)号：US09202015B2

公开(公告)日：2015-12-01

申请号：US12650579

申请日：2009-12-31

申请人： Sham M. Datta ,  Ernie F. Brickell ,  Mohan J. Kumar

发明人： Sham M. Datta ,  Ernie F. Brickell ,  Mohan J. Kumar

IPC分类号： G06F21/00 ,  G06F21/57 ,  G06F21/71

CPC分类号： G06F21/00 ,  G06F21/57 ,  G06F21/572 ,  G06F21/71 ,  G06F2221/2149 ,  G06F2221/2153

摘要： Systems, apparatuses, and methods, and for entering a secured system environment using multiple authenticated code modules are disclosed. In one embodiment, a processor includes a decoder and control logic. The decoder is to decode a secured enter instruction. The control logic is to find an entry corresponding to the processor in a match table in a master authenticated code module and to read a master header and an individual authenticated code module from the master authenticated code module in response to decoding the secured enter instruction.

摘要翻译： 公开了系统，装置和方法以及使用多个认证代码模块输入安全系统环境。 在一个实施例中，处理器包括解码器和控制逻辑。 解码器是对安全的输入指令进行解码。 控制逻辑是在主认证代码模块的匹配表中找到与处理器相对应的条目，并且响应于对安全的进入指令进行解码，从主认证代码模块读取主标题和单独的认证代码模块。