公开(公告)号：US5347493A

公开(公告)日：1994-09-13

申请号：US938731

申请日：1992-08-31

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G11C17/18 ,  G11C8/10 ,  G11C17/12 ,  G11C8/00

CPC分类号： G11C17/123 ,  G11C17/12 ,  G11C8/10

摘要： A decoder for a ROM matrix organized in selectable NAND parcels of cells utilizes four selection circuits driven through five buses for implementing a two-level decoding, thus driving less than all of the rows through a plurality of selectable drivers. The architecture of the row decoder, based on a subdivision into a plurality of row drivers renders the circuitry physically compatible with the geometrical constraints imposed by a particularly small pitch of the cells. Subdivision of row drivers has positive effects also on access time, reliability and overall performance of the memory as compared to a memory provided with a decoder of the prior art driving in parallel all the homonymous rows of all the selectable NAND parcels of cells.

摘要翻译： 用于组合在可选择的NAND小区中的ROM矩阵的解码器利用通过五个总线驱动的四个选择电路来实现两级解码，从而通过多个可选驱动器驱动小于所有行。 行解码器的架构基于对多个行驱动器的细分，使得电路与由单元的特别小间距施加的几何约束物理上兼容。 与现有技术的解码器配备的存储器相比，行驱动器的细分对存取时间，可靠性和整体性能也具有积极的影响，并行驱动所有可选择的NAND包细胞的所有同行。

公开(公告)号：US5270590A

公开(公告)日：1993-12-14

申请号：US806118

申请日：1991-12-12

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G11C17/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28 ,  G11C29/00 ,  G11C29/56 ,  H03F3/45 ,  H03K5/22

CPC分类号： G11C16/28 ,  G11C7/14

摘要： The sense circuit, for recognizing the virgin or programmed status of cells in storage devices, comprises a differential amplifier having a first input connected to a number of selectable matrix cells, through a first uncoupling circuit, a second input connected to a number of selectable reference virgin cells through a second uncoupling circuit, respective matrix and reference load transistors connected between each input of the amplifier and a supply voltage, and a current generator connected in parallel to the matrix cells and controlled by the first input of the amplifier to draw a current equal to a predetermined fraction of the current flowing through said first input.

公开(公告)号：US08759915B2

公开(公告)日：2014-06-24

申请号：US12293534

申请日：2006-03-20

申请人： Paolo Rolandi ,  Cristiano Calligaro ,  Luigi Pascucci

发明人： Paolo Rolandi ,  Cristiano Calligaro ,  Luigi Pascucci

IPC分类号： H01L21/02

CPC分类号： H01L27/11551 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/7832

摘要： Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.

摘要翻译： 由半导体材料的第一导电条形成的半导体器件; 半导体材料的控制栅极区域，面对第一导电条的沟道部分，以及布置在第一导电条和控制栅极区域之间的绝缘区域。 第一导电带包括具有第一导电类型的导线和具有彼此相邻并且彼此电接触布置的第二导电类型的控制线，并且导线形成沟道部分，第一导电部分和第二导电 部分布置在通道部分的相对侧上。

公开(公告)号：US08030765B2

公开(公告)日：2011-10-04

申请号：US12401464

申请日：2009-03-10

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： H01L23/48

CPC分类号： H01L23/50 ,  H01L23/525 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that includes a plurality of address pads and respective supply pins. The method includes: realizing at least one configuration terminal having a first and a second portion structurally independent and connected to at least one contact terminal; providing the contact of such first and second portions with respective terminals; and configuring the device by a short-circuiting of the contact terminal with at least one of said terminals.

摘要翻译： 用于集成器件的配置端子包括结构独立并连接到相应的第一和第二端子的第一和第二部分，并且其具有适合于选择性地连接到这样的第一和第二端子的至少一个接触端子。 此外，一种方法构成了包括多个地址焊盘和相应的电源引脚的集成器件。 该方法包括：实现至少一个配置终端，其具有在结构上独立且连接到至少一个接触终端的第一和第二部分; 提供这样的第一和第二部分与相应的端子的接触; 以及通过所述接触端子与至少一个所述端子的短路来配置所述装置。

公开(公告)号：US20090180328A1

公开(公告)日：2009-07-16

申请号：US12409740

申请日：2009-03-24

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C16/06

CPC分类号： G11C5/066 ,  G11C7/1018 ,  G11C7/1045 ,  G11C16/0483 ,  G11C16/08 ,  G11C2207/105

摘要： A method for accessing, in reading, programming, and erasing a semiconductor-integrated non-volatile memory device of the Flash EEPROM type with a NAND architecture having at least one memory matrix organized in rows or word lines and columns or bit lines, and wherein, for the memory, a plurality of additional address pins are provided. The method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with the additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to the additional address pins are also provided to allow a double addressing mode, sequential and in parallel.

摘要翻译： 一种用于以具有至少一个以行或字线和列或位线组织的存储矩阵的NAND架构来访问，读取，编程和擦除闪存EEPROM类型的半导体集成非易失性存储器件的方法，其中 为了存储器，提供了多个附加的地址引脚。 该方法提供异步类型的访问协议和扩展类型的协议，允许通过在两个连续的时钟脉冲中加载与附加引脚相关联的地址寄存器来直接和并行地寻址存储器扩展部分。 还提供了第三个多次访问模式和引用附加地址引脚的并行附加总线，以允许双寻址模式，顺序和并行。

公开(公告)号：US07397702B2

公开(公告)日：2008-07-08

申请号：US11178240

申请日：2005-07-08

申请人： Paolo Rolandi ,  Luigi Pascucci

发明人： Paolo Rolandi ,  Luigi Pascucci

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/28 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5634

摘要： A read/verify circuit for multilevel memory cells includes: a read terminal selectively connectable to a plurality of array cells, having respective array threshold voltages; a plurality of reference cells, having respective reference threshold voltages; and a plurality of threshold-detection circuits, for detecting the array thresholds and the reference thresholds. In particular, the read terminal and the reference cells are each connected to a respective threshold-detection circuit. Each threshold-detection circuit is provided with a respective detector element of a resistive type, set so as to be traversed by a current response to turning-on of the respective array cell or reference cell associated thereto.

摘要翻译： 用于多电平存储器单元的读/验电路包括：可选择地连接到具有相应阵列阈值电压的多个阵列单元的读终端; 多个参考单元，具有各自的参考阈值电压; 以及用于检测阵列阈值和参考阈值的多个阈值检测电路。 特别地，读取终端和参考单元各自连接到相应的阈值检测电路。 每个阈值检测电路设置有电阻型的相应检测器元件，其被设置为通过与其相关联的相应阵列单元或参考单元的导通的电流响应来遍历。

公开(公告)号：US20070279996A1

公开(公告)日：2007-12-06

申请号：US11695552

申请日：2007-04-02

申请人： Paolo Rolandi ,  Luigi Pascucci

发明人： Paolo Rolandi ,  Luigi Pascucci

IPC分类号： G11C16/06

CPC分类号： G11C16/3431 ,  G11C11/5628 ,  G11C16/3418

摘要： A refresh circuit for refreshing a memory device is proposed. The refresh circuit includes: reading means for reading a set of memory cells, the reading means including means for applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells each one having a reference threshold voltage, means for detecting the reaching of a comparison current by a cell current of each memory cell and by a reference current of each reference cell, and means for determining a condition of each memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and the reference currents, and writing means for applying a writing voltage to at least one selected of the memory cells; the refresh circuit further includes control means for enabling the writing means during at least part of the application of the biasing voltage after the determination of the condition of each selected memory cell.

摘要翻译： 提出了刷新存储器件的刷新电路。 刷新电路包括：用于读取一组存储单元的读取装置，所述读取装置包括用于向存储单元施加具有基本上单调的时间模式的偏置电压的装置和具有参考阈值电压的一组参考单元， 用于通过每个存储单元的单元电流和每个参考单元的参考电流来检测比较电流达到的装置，以及用于根据达到比较电流的时间关系确定每个存储单元的状态的装置 对应的单元电流和参考电流;以及写入装置，用于向至少一个选择的存储单元施加写入电压; 刷新电路还包括控制装置，用于在确定每个所选择的存储单元的状态之后，在施加偏置电压的至少一部分期间使写入装置能够使能。

公开(公告)号：US07181592B2

公开(公告)日：2007-02-20

申请号：US10245795

申请日：2002-09-16

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G06F12/00

CPC分类号： G06F12/0223 ,  G06F12/06

摘要： A pointer circuit for pointing to elements in at least one collection of elements comprises a base pointer for providing a first binary-coded value defining a first address of an element in the collection. The pointer circuit also comprises a binary shift circuit receiving the first binary-coded value provided by the base pointer and a second binary-coded value defining a shift value. The binary shift circuit combines the first and second binary-coded values to provide a third binary-coded value defining a second address of an element in the collection differing from the first address by the shift value. A shift-value generator fed by the first binary-coded value generates the second binary-coded value depending on the first binary-coded value, so that a generated shift value takes into account shift values corresponding to first binary-coded values preceding a current first binary-coded value in a prescribed first binary-coded value progression order.

摘要翻译： 用于指向至少一个元素集合中的元素的指针电路包括用于提供定义集合中的元素的第一地址的第一二进制编码值的基指针。 指针电路还包括接收由基本指针提供的第一二进制编码值的二进制移位电路和定义移位值的第二二进制编码值。 二进制移位电路组合第一和第二二进制编码值以提供定义集合中的元素的第二地址的第三二进制编码值，该第一地址与第一地址不同，移位值不同。 通过第一二进制编码值馈送的移位值生成器根据第一二进制编码值产生第二二进制编码值，使得生成的移位值考虑与当前值之前的第一二进制编码值相对应的移位值 以规定的第一二进制编码值进度顺序的第一二进制编码值。

公开(公告)号：US20060268650A1

公开(公告)日：2006-11-30

申请号：US11434564

申请日：2006-05-15

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C16/08

摘要： A row decoder circuit is described of the type comprising at least one input stage connected to a first supply voltage reference and to an output stage connected to a second supply voltage reference, the output stage having at least one output terminal connected to a word line of a memory matrix. The row decoder circuit further comprises a biasing device, connected to a third supply voltage reference and comprising at least one generator of a negative voltage connected to a divider, in turn connected to a first biasing terminal of the biasing device. In particular, the first biasing terminal is connected to at least one input stage in correspondence with bulk terminals of MOS transistors comprised in the input stage and it is suitable for supplying it with a first negative voltage.

公开(公告)号：US20060239076A1

公开(公告)日：2006-10-26

申请号：US11279385

申请日：2006-04-11

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C16/04

CPC分类号： G11C16/08 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  Y10T29/49002

摘要： A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

摘要翻译： 非易失性存储器电子器件集成在半导体上，并且具有闪存EEPROM类型，其具有NAND架构，其包括分成物理扇区的至少一个存储器矩阵，其被设计为最小的可擦除单元，并且被组织成行或字线和列或 位线的存储单元。 给定物理扇区的至少一行或字线电连接到相邻物理扇区的至少一行或字线，以形成可擦除的单个逻辑扇区，其中一对连接的相应小区的源终端 行指向源行的相同选择行。