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61.发明申请公开(公告)号：US20140068135A1
公开(公告)日：2014-03-06
申请号：US14011009
申请日：2013-08-27
IPC分类号： G06F13/40
CPC分类号： G06F13/4027 , G06F1/3203 , G06F13/20 , G06F13/4295 , G06N99/005 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有事务层和链路层的协议栈。 另外，第一物理（PHY）单元被耦合到协议栈，以经由物理链路提供处理器和耦合到处理器的设备之间的通信，其中第一PHY单元是低功率通信协议，并且包括第一物理 单位电路。 反过来，第二PHY单元被耦合到协议栈，以经由耦合在与物理链路分离的多核处理器和设备之间的边带信道来提供处理器和设备之间的通信，其中第二PHY单元包括第二物理单元 电路。 描述和要求保护其他实施例。
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公开(公告)号：US08612060B2
公开(公告)日：2013-12-17
申请号：US12890439
申请日：2010-09-24
CPC分类号： G06Q30/0241 , G06F1/266
摘要： Methods and systems may include an apparatus having a power line interface and a controller with management logic. The management logic can manage the power delivery policies of devices connected to the power line interface based on changes in the power delivery capability of the apparatus.
摘要翻译： 方法和系统可以包括具有电力线接口的装置和具有管理逻辑的控制器。 管理逻辑可以基于设备的功率传递能力的变化来管理连接到电力线接口的设备的功率传递策略。
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公开(公告)号：US08549205B1
公开(公告)日：2013-10-01
申请号：US13477304
申请日：2012-05-22
IPC分类号： G06F13/20
CPC分类号： G06F13/4027 , G06F1/3203 , G06F13/20 , G06F13/4295 , G06N99/005 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.
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公开(公告)号：US20130132636A1
公开(公告)日：2013-05-23
申请号：US13690931
申请日：2012-11-30
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/42
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
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公开(公告)号：US20130091317A1
公开(公告)日：2013-04-11
申请号：US13691016
申请日：2012-11-30
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/40
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
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66.发明申请MECHANISM TO FLEXIBLY SUPPORT MULTIPLE DEVICE NUMBERS ON POINT-TO-POINT INTERCONNECT UPSTREAM PORTS 有权灵活支持点到点互连上桥端口的多个设备号码的机制公开(公告)号：US20130013829A1
公开(公告)日：2013-01-10
申请号：US13619612
申请日：2012-09-14
申请人： David J. Harriman
发明人： David J. Harriman
IPC分类号： G06F13/14
CPC分类号： G06F13/4022
摘要： A method and apparatus for supporting multiple device numbers on point-to-point interconnect upstream ports. In one embodiment, the method includes a downstream component (DC) that performs discovery of internal device components of the DC during initialization of the DC. Subsequent to the discovery of internal devices of the DC, the DC may issue a multiple device number (MDN) request to an upstream component (UC) of the DC. In one embodiment, the MDN request may include an indication that the DC supports a “multiple device number capability,” as well as a quantity of the internal device components of the DC. The DC may receive an acknowledgement MDN from the UC to indicate a quantity of device numbers allocated to the DC. Subsequently, the DC may assign device numbers to the internal device components of the DC according to configuration requests received from the UC. Other embodiments are described and claimed.
摘要翻译： 一种用于在点对点互连上游端口上支持多个设备编号的方法和装置。 在一个实施例中，该方法包括在初始化DC期间执行DC的内部设备组件的发现的下游组件（DC）。 在发现DC的内部设备之后，DC可以向DC的上游组件（UC）发出多个设备号（MDN）请求。 在一个实施例中，MDN请求可以包括DC支持多设备号码能力的指示以及DC的内部设备组件的数量。 DC可以从UC接收确认MDN以指示分配给DC的设备号的数量。 随后，DC可以根据从UC接收到的配置请求，将设备编号分配给DC的内部设备组件。 描述和要求保护其他实施例。
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公开(公告)号：US20120078690A1
公开(公告)日：2012-03-29
申请号：US12890439
申请日：2010-09-24
CPC分类号： G06Q30/0241 , G06F1/266
摘要： Methods and systems may include an apparatus having a power line interface and a controller with management logic. The management logic can manage the power delivery policies of devices connected to the power line interface based on changes in the power delivery capability of the apparatus.
摘要翻译： 方法和系统可以包括具有电力线接口的装置和具有管理逻辑的控制器。 管理逻辑可以基于设备的功率传递能力的变化来管理连接到电力线接口的设备的功率传递策略。
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68.发明授权Opportunistic improvement of MMIO request handling based on target reporting of space requirements 有权基于空间要求的目标报告，MMIO请求处理的机会性改进公开(公告)号：US08055805B2
公开(公告)日：2011-11-08
申请号：US12415913
申请日：2009-03-31
申请人： David J. Harriman , Andrew F. Glew
发明人： David J. Harriman , Andrew F. Glew
IPC分类号： G06F3/00
CPC分类号： G06F13/16 , G06F9/46 , G06F12/02 , G06F12/063 , G06F12/1027 , G06F13/14 , G06F15/16 , G06F2212/654
摘要： Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed.
摘要翻译： 描述了存储映射输入/输出（MMIO）请求处理的机会性改进的方法和装置（例如，基于空间要求的目标报告）。 在一个实施例中，处理器中的逻辑可以检测要从输入/输出（I / O）设备发送的消息中的一个或多个位。 一个或多个比特可以指示对应于I / O设备的一个或多个属性的存储器映射I / O（MMIO）信息。 还公开了其他实施例。
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69.发明授权Mechanism to flexibly support multiple device numbers on point-to-point interconnect upstream ports 有权在点对点互连上游端口上灵活支持多个设备编号的机制公开(公告)号：US07660922B2
公开(公告)日：2010-02-09
申请号：US11433018
申请日：2006-05-12
申请人： David J. Harriman
发明人： David J. Harriman
CPC分类号： G06F13/4022
摘要： A method and apparatus for supporting multiple device numbers on point-to-point interconnect upstream ports. In one embodiment, the method includes a downstream component (DC) that performs discovery of internal device components of the DC during initialization of the DC. Subsequent to the discovery of internal devices of the DC, the DC may issue a multiple device number (MDN) request to an upstream component (UC) of the DC. In one embodiment, the MDN request may include an indication that the DC supports a “multiple device number capability,” as well as a quantity of the internal device components of the DC. The DC may receive an acknowledgement MDN from the UC to indicate a quantity of device numbers allocated to the DC. Subsequently, the DC may assign device numbers to the internal device components of the DC according to configuration requests received from the UC. Other embodiments are described and claimed.
摘要翻译： 一种用于在点对点互连上游端口上支持多个设备编号的方法和装置。 在一个实施例中，该方法包括在初始化DC期间执行DC的内部设备组件的发现的下游组件（DC）。 在发现DC的内部设备之后，DC可以向DC的上游组件（UC）发出多个设备号（MDN）请求。 在一个实施例中，MDN请求可以包括DC支持“多设备号码能力”的指示以及DC的内部设备组件的数量。 DC可以从UC接收确认MDN以指示分配给DC的设备号的数量。 随后，DC可以根据从UC接收到的配置请求，将设备编号分配给DC的内部设备组件。 描述和要求保护其他实施例。
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公开(公告)号：US06499085B2
公开(公告)日：2002-12-24
申请号：US09752846
申请日：2000-12-29
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F12/0835
摘要： A system is described for servicing a full cache line in response to a partial cache line request. The system includes a storage to store at least one cache line, a hit/miss detector, and a data mover. The hit/miss detector receives a partial cache line read request from a requesting agent and dispatches a fetch request to a memory device to fetch a full cache line data that contains data requested in the partial cache line read request from the requesting agent. The data mover loads the storage with the full cache line data returned from the memory device and forwards a portion of the full cache line data requested by the requesting agent. If data specified in a subsequent partial cache line request from the requesting agent is contained within the full cache line data specified in the previously dispatched fetch request, the hit/miss detector will send a command to the data mover to forward another portion of the full cache line data stored in the storage to the requesting agent. In one embodiment, the system also includes a write combining logic to combine two or more consecutive write requests that meet defined conditions into a single write request.
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