公开(公告)号：US11688473B2

公开(公告)日：2023-06-27

申请号：US16986827

申请日：2020-08-06

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Scott Anthony Stoller ,  Jung Sheng Hoei ,  Ashutosh Malshe ,  Gianni Stephen Alsasua ,  Kishore Kumar Muchherla

IPC: G11C16/34 ,  G11C16/28 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3427 ,  G11C16/3431 ,  G11C16/0483

Abstract: NAND memory devices are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.

公开(公告)号：US11682446B2

公开(公告)日：2023-06-20

申请号：US17679656

申请日：2022-02-24

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Harish R. Singidi ,  Ashutosh Malshe ,  Gianni S. Alsasua

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/409 ,  G11C29/44

CPC classification number: G11C11/40622 ,  G11C11/409 ,  G11C11/4085 ,  G11C29/44

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing a first data integrity check on memory pages of a first set of wordlines of the memory device; performing a second data integrity check on memory pages of a second set of wordlines comprising a plurality of wordlines from the first set of wordlines; identifying, among the first set of wordlines and the second set of wordlines, a wordline having a first data state metric value obtained from the first data integrity check equal to a second data state metric value obtained from the second data integrity check; and performing a third data integrity check on a third set of wordlines comprising at least one wordline from the first set of wordlines, wherein the third data integrity check excludes the identified wordline.

公开(公告)号：US20230168829A1

公开(公告)日：2023-06-01

申请号：US18104007

申请日：2023-01-31

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore K. Muchherla

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0679 ,  G06F3/0604 ,  G06F3/0659

Abstract: A method includes determining respective valid translation unit counts of a block of non-volatile memory cells over a period of time, determining a rate of change of the respective valid translation unit counts of the block of non-volatile memory cells over the period of time, comparing the rate of change of the valid translation unit counts to a bin transition rate, and based on comparing the rate of change of the valid translation unit counts to the bin transition rate, performing a media management operation on the block of non-volatile memory cells.

公开(公告)号：US11656931B2

公开(公告)日：2023-05-23

申请号：US17531960

申请日：2021-11-22

Applicant: Micron Technology, Inc.

Inventor： Harish R. Singidi ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

IPC: G06F11/00 ,  G06F11/07 ,  G11C29/00

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0757 ,  G06F11/0793 ,  G11C29/883

Abstract: A method includes obtaining a first operation execution time corresponding to an operation performed on a page of a first data unit of a memory device, determining whether the first operation execution time satisfies a condition that is based on a second operation execution time, wherein the second operation execution time is indicative of lack of defect in at least a second data unit of the memory device, and responsive to determining that the first operation execution time satisfies the condition that is based on the second operation execution time, initiating a defect scan operation of at least a subset of pages of the first data unit.

公开(公告)号：US20230110545A1

公开(公告)日：2023-04-13

申请号：US18079843

申请日：2022-12-12

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Harish R. Singidi ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe ,  Sampath K. Ratnam

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G11C16/30 ,  G11C16/08

Abstract: A request to perform a secure erase operation for a memory component can be received. A voltage level of a pass voltage that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied during a program operation to at least one wordline of the memory component to perform the secure erase operation. The voltage pulse can exceed the pass voltage applied to the unselected wordlines of the memory component during the read operation.

公开(公告)号：US11615858B2

公开(公告)日：2023-03-28

申请号：US17341830

申请日：2021-06-08

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore K. Muchherla

IPC: G06F11/10 ,  G06F11/34 ,  G06F16/11 ,  G06F16/16 ,  G06F16/17 ,  G06F3/06 ,  G06F12/02 ,  G11C16/34 ,  G11C16/10 ,  G11C16/16 ,  G06F12/0891 ,  G11C16/26

Abstract: A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.

公开(公告)号：US11561722B2

公开(公告)日：2023-01-24

申请号：US17002374

申请日：2020-08-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Harish R Singidi ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

IPC: G06F3/06 ,  H03M7/30 ,  G06F11/10

Abstract: A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device, to store host data in the page of the data unit. The processing device further generates a parity page for the host data stored in the page of the data unit and adds the parity page to parity data stored at a parity data storage location. Responsive to determining that a first size of the stored parity data satisfies a first condition, the processing device initiates execution of a compression algorithm to compress the stored parity data. Responsive to determining that a second size of the parity data resulting from the execution of the compression algorithm satisfies a second condition, the processing device performs a scan operation to release at least a subset of the stored parity data.

公开(公告)号：US20220383962A1

公开(公告)日：2022-12-01

申请号：US17886884

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Harish R. Singidi ,  Renato C. Padilla ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe ,  Sampath K. Ratnam

IPC: G11C16/34 ,  G11C16/08 ,  G06F11/30 ,  G06F11/07

Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. Responsive to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first set of wordlines of the data block, the first set comprising first alternating pairs of adjacent wordlines.

公开(公告)号：US20220343984A1

公开(公告)日：2022-10-27

申请号：US17859926

申请日：2022-07-07

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore K. Muchherla

IPC: G11C16/34 ,  G11C16/26 ,  G06F12/02 ,  G11C16/16 ,  G11C16/32

Abstract: A method includes determining a first valid translation unit count (VTC) for a first block of memory cells, determining a second VTC for a second block of memory cells when the first VTC is below a VTC threshold corresponding to performance of a memory management operation, consolidating the first VTC and the second VTC when the consolidated first VTC and the second VTC equal or exceed the VTC threshold corresponding to the performance of the memory management operation, and executing the memory management operation utilizing the consolidated first VTC and the second VTC.

公开(公告)号：US20220334756A1

公开(公告)日：2022-10-20

申请号：US17235216

申请日：2021-04-20

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Giuseppina Puzzilli ,  Saeed Sharifi Tehrani

IPC: G06F3/06

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, receiving a read request to perform a read operation on a block of the memory device; determining whether an entry corresponding to the block is stored in a data structure associated with the memory device; responsive to the entry being stored in the data structure, incrementing a counter associated with the block to track a number of read operations performed on the block of the memory device; resetting a timer associated with the block to an initial value, wherein the timer is to track a period of time that elapses since the read operation was performed on the block of the memory device; determining that the counter and the timer satisfy a first criterion; and responsive to determining that the counter and the timer satisfy the first criterion, removing the entry corresponding to the block from the data structure associated with the memory device.