公开(公告)号：US11862280B2

公开(公告)日：2024-01-02

申请号：US17970759

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Stephen W. Russell ,  Stephen H. Tang

IPC: G11C5/06 ,  G11C8/10 ,  H01L23/50 ,  H10B99/00

CPC classification number: G11C5/06 ,  G11C8/10 ,  H01L23/50 ,  H10B99/00

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

公开(公告)号：US20230354721A1

公开(公告)日：2023-11-02

申请号：US17660939

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Stephen W. Russell ,  Enrico Varesi ,  Lorenzo Fratin

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1616 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/1683

Abstract: Methods, systems, and devices for memory cell formation in three dimensional memory arrays using atomic layer deposition (ALD) are described. The method may include depositing a stack of layers over a substrate and forming multiple piers through the stacks of layers. The method may further include forming multiple cavities through the stacks of layers and forming multiple voids between layers of the stacks of layers. Additionally, the method may include forming multiple word lines based on depositing a conductive material in the voids and forming multiple memory cells based on depositing an active material on an inside surface of the cavities using ALD.

公开(公告)号：US20230309426A1

公开(公告)日：2023-09-28

申请号：US17656280

申请日：2022-03-24

Applicant: Micron Technology, Inc.

Inventor： Stephen W. Russell ,  Enrico Varesi ,  David H. Wells ,  Paolo Fantini ,  Lorenzo Fratin

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  G11C13/0028 ,  H01L27/2481 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/1608

Abstract: Methods, systems, and devices for sparse piers for three-dimensional memory arrays are described. A semiconductor device, such as a memory die, may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide mechanical support for subsequent processing. For example, a memory die may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. In some examples, the alternating layers may be formed into one or more pairs of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns to provide mechanical support between instances of the cross-sectional patterns, or between layers of the cross-sectional patterns (e.g., when one or more layers are removed from the cross-sectional patterns), or both.

公开(公告)号：US20230170015A1

公开(公告)日：2023-06-01

申请号：US17456968

申请日：2021-11-30

Applicant: Micron Technology, Inc.

Inventor： Ahmed Nayaz Noemaun ,  Chandra S. Danana ,  Durga P. Panda ,  Luca Laurin ,  Michael J. Irwin ,  Rekha Chithra Thomas ,  Sara Vigano ,  Stephen W. Russell ,  Zia A. Shafi

IPC: G11C13/00 ,  H01L27/24 ,  H01L29/423

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  H01L27/2481 ,  H01L29/4236 ,  H01L29/42376 ,  G11C2213/71

Abstract: Methods, systems, and devices for memory device decoder configurations are described. A memory device may include an array of memory cells and decoder circuits. The array may include one or more memory cells coupled with an access line, and a decoder circuit may be configured to bias the access line to one or more voltages. The decoder circuit may include a first transistor coupled with the access line and a second transistor coupled with the access line. The first transistor may be a planar transistor having a first gate electrode formed on a substrate, and the second transistor may be a trench transistor having a second gate electrode that extends into a cavity of the substrate, where a length of a first gate electrode may be greater than a length of the second gate electrode.

公开(公告)号：US11501803B2

公开(公告)日：2022-11-15

申请号：US17062024

申请日：2020-10-02

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Stephen W. Russell ,  Stephen H. Tang

IPC: G11C5/06 ,  H01L27/105 ,  G11C8/10 ,  H01L23/50

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

公开(公告)号：US20210359089A1

公开(公告)日：2021-11-18

申请号：US15930090

申请日：2020-05-12

Applicant: Micron Technology, Inc.

Inventor： Ahmed Nayaz Noemaun ,  Stephen W. Russell ,  Tao D. Nguyen ,  Santanu Sarkar

IPC: H01L29/40 ,  H01L21/82 ,  H01L29/66

Abstract: Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.

公开(公告)号：US20210351125A1

公开(公告)日：2021-11-11

申请号：US17379257

申请日：2021-07-19

Applicant: Micron Technology, Inc.

Inventor： Stephen W. Russell ,  Fabio Pellizzer ,  Lorenzo Fratin

IPC: H01L23/522 ,  H01L21/768

Abstract: Methods for forming microelectronic device structures include forming interconnects that are self-aligned with both a lower conductive structure and an upper conductive structure. At least one lateral dimension of an interconnect is defined upon subtractively patterning the lower conductive structure along with a first sacrificial material. At least one other lateral dimension of the interconnect is defined by patterning a second sacrificial material or by an opening formed in a dielectric material through which the interconnect will extend. A portion of the first sacrificial material, exposed within the opening through the dielectric material, along with the second sacrificial material are removed and replaced with conductive material(s) to integrally form the interconnect and the upper conductive structure. The interconnect occupies a volume between vertically overlapping areas of the lower conductive structure and the upper conductive structure, where such overlapping areas coincide with the opening through the dielectric material.

公开(公告)号：US20210288050A1

公开(公告)日：2021-09-16

申请号：US17332640

申请日：2021-05-27

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Stephen W. Russell ,  Stephen H. Tang

IPC: H01L27/105 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/40

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

公开(公告)号：US11069610B2

公开(公告)日：2021-07-20

申请号：US16653442

申请日：2019-10-15

Applicant: Micron Technology, Inc.

Inventor： Stephen W. Russell ,  Fabio Pellizzer ,  Lorenzo Fratin

IPC: H01L21/00 ,  H01L23/522 ,  H01L21/768

Abstract: Methods for forming microelectronic device structures include forming interconnects that are self-aligned with both a lower conductive structure and an upper conductive structure. At least one lateral dimension of an interconnect is defined upon subtractively patterning the lower conductive structure along with a first sacrificial material. At least one other lateral dimension of the interconnect is defined by patterning a second sacrificial material or by an opening formed in a dielectric material through which the interconnect will extend. A portion of the first sacrificial material, exposed within the opening through the dielectric material, along with the second sacrificial material are removed and replaced with conductive material(s) to integrally form the interconnect and the upper conductive structure. The interconnect occupies a volume between vertically overlapping areas of the lower conductive structure and the upper conductive structure, where such overlapping areas coincide with the opening through the dielectric material.

公开(公告)号：US10991425B2

公开(公告)日：2021-04-27

申请号：US16102494

申请日：2018-08-13

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Stephen W. Russell

IPC: H01L47/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: Methods, systems, and devices for access line grain modulation in a memory device are described. A memory cell stack in a cross-point memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A barrier material may be formed above the memory cell stack. The barrier material may initially have an undulating top surface. In some cases, the top surface of the barrier material may be planarized. After the top surface of the barrier material is planarized, a metal layer for an access line may be formed on the top surface of the barrier material. Planarizing the top surface of the barrier material may impact the grain size of the metal layer. In some cases, planarizing the top surface of the barrier material may decrease the resistivity of access lines formed from the metal layer and thus increase current delivery throughout the memory device.