公开(公告)号：US20210026542A1

公开(公告)日：2021-01-28

申请号：US16522454

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Rachael R. Carlson ,  Aparna U. Limaye ,  Diana C. Majerus ,  Debra M. Bell ,  Shea M. Morrison

IPC: G06F3/06 ,  G11C29/44 ,  G06F21/79

Abstract: Apparatuses and methods related to memory authentication. Memory devices can be authenticated utilizing authentication codes. An authentication code can be generated based on information stored in a fuse array of the memory device. The authentication code can be stored in the memory device. The stored authentication code can be compared to a captured authentication code based on fuse array information broadcast to memory components of the memory device. The authenticity of the memory device can be determined based on the comparison and can result in placing the memory device in an unlocked state.

公开(公告)号：US10885967B2

公开(公告)日：2021-01-05

申请号：US16247277

申请日：2019-01-14

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Debra M. Bell ,  George B. Raad ,  Brian P. Callaway ,  Joshua E. Alzheimer

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/403

Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.

公开(公告)号：US20200342931A1

公开(公告)日：2020-10-29

申请号：US16926476

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： James R. Rehmeyer ,  George B. Raad ,  Debra M. Bell ,  Markus H. Geiger ,  Anthony D. Veches

IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/406

Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.

公开(公告)号：US20200301590A1

公开(公告)日：2020-09-24

申请号：US16361864

申请日：2019-03-22

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Naveh Malihi

IPC: G06F3/06 ,  G11C7/06

Abstract: Apparatuses and methods related to updating data lines for data generation in, for example, a memory device or a computing system that includes a memory device. Updating data lines can include updating a plurality of data lines. The plurality of data lines can provide data form the memory array responsive to a receipt of the access command. The plurality of data lines can also be updated responsive to a determination that an access command received at a memory device is unauthorized.

公开(公告)号：US10762946B2

公开(公告)日：2020-09-01

申请号：US16237013

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C11/406 ,  G11C11/4074 ,  G11C16/10 ,  G11C11/4072

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a plurality of memory cells arranged in a plurality of memory regions and (ii) inhibit circuitry. In some embodiments, the inhibit circuitry is configured to disable one or more memory regions of the plurality of memory regions from receiving refresh commands such that memory cells of the one or more memory regions are not refreshed during refresh operations of the memory device. In these and other embodiments, the memory controller is configured to track memory regions that include utilized memory cells and/or to write data to the memory regions in accordance with a programming sequence of the memory device.

公开(公告)号：US10748600B2

公开(公告)日：2020-08-18

申请号：US16216894

申请日：2018-12-11

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  George B. Raad ,  Debra M. Bell ,  Markus H. Geiger ,  Anthony D. Veches

IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/406

Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.

公开(公告)号：US20190096894A1

公开(公告)日：2019-03-28

申请号：US16204409

申请日：2018-11-29

Applicant: Micron Technology Inc.

Inventor： Debra M. Bell ,  Scott J. Derner

IPC: H01L27/11 ,  H01L21/762 ,  G11C11/412 ,  G11C11/419

CPC classification number: H01L27/1112 ,  G11C11/412 ,  G11C11/419 ,  H01L21/76202 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/1104 ,  H01L27/1108

Abstract: Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.

公开(公告)号：US20180032458A1

公开(公告)日：2018-02-01

申请号：US15220177

申请日：2016-07-26

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell

IPC: G06F13/366 ,  G06F13/28 ,  G06F13/24

CPC classification number: G06F13/366 ,  G06F11/00 ,  G06F13/1668 ,  G06F13/24 ,  G06F13/287 ,  G11C7/00 ,  G11C7/24

Abstract: The present disclosure includes apparatuses and methods related to accessing status information. One example apparatus comprises a host and a memory device coupled to the host. The memory device includes a controller configured to provide, to a status arbiter, a status signal indicating whether a status register of the controller contains generated status information. Responsive to the status signal indicating that the status register contains the generated status information, the controller can also provide the status information from the controller to the status arbiter via a status intermediary.

公开(公告)号：US20180012636A1

公开(公告)日：2018-01-11

申请号：US15205885

申请日：2016-07-08

Applicant: Micron Technology, Inc.

Inventor： Joshua E. Alzheimer ,  Debra M. Bell

IPC: G11C7/06 ,  G11C7/22

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091

Abstract: Examples include apparatuses and methods related to scan chain operation in sensing circuitry. A number of embodiments include an apparatus comprising an array of memory cells coupled to sensing circuitry having a sense amplifier and a compute component, the sensing circuitry to receive a scan vector and perform a scan chain operation on the scan vector.

公开(公告)号：US09047978B2

公开(公告)日：2015-06-02

申请号：US14010120

申请日：2013-08-26

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C7/00 ,  G11C11/406 ,  G11C7/10

CPC classification number: G11C11/406 ,  G11C7/1012

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

Abstract translation: 本文公开了用于选择行刷新的装置和方法。 示例性装置可以包括刷新控制电路。 刷新控制电路可以被配置为从地址总线接收与目标多个存储器单元相关联的目标地址。 刷新控制电路还可以被配置为至少部分地响应于确定已经发生了多个刷新操作来向地址总线提供邻近地址。 在一些示例中，与邻近地址相关联的多个存储单元可以是与目标多个存储单元相邻的多个存储单元。