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104 条记录 (耗时 0.039 秒)

    Integrated circuit system with metal and semi-conducting gate
    61.
    发明授权
    Integrated circuit system with metal and semi-conducting gate 有权
    具有金属和半导体栅极的集成电路系统

    公开(公告)号：US08283718B2

    公开(公告)日：2012-10-09

    申请号：US11611856

    申请日：2006-12-16

    申请人： Angela T. Hui ,  Mark S. Chang ,  Kuo-Tung Chang ,  Scott A. Bell

    发明人： Angela T. Hui ,  Mark S. Chang ,  Kuo-Tung Chang ,  Scott A. Bell

    IPC分类号： H01L29/792

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.

    摘要翻译： 提供了一种用于形成集成电路系统的方法，包括在衬底上形成半导电层，形成间隔层叠层，其间隔填充物与半导体层相邻，间隙填料上形成层间电介质，形成过渡层 该层在半导体层上具有凹陷并且与间隔物堆叠相邻，并且在凹部中形成金属层。

    GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPROACH TO TARGET CD FOR SELECTED TRANSISTORS
    62.
    发明申请
    GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPROACH TO TARGET CD FOR SELECTED TRANSISTORS 有权
    使用蚀刻或干蚀刻方法对选定的晶体管的目标光盘进行栅格扫描过程

    公开(公告)号：US20120032308A1

    公开(公告)日：2012-02-09

    申请号：US13278343

    申请日：2011-10-21

    申请人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

    发明人： Bradley M. Davis ,  Jihwan Choi ,  Angela T. Hui

    IPC分类号： H01L21/306 ,  H01L29/06

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/823456

    摘要： Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

    摘要翻译： 公开了用于在半导体器件中靶向所选晶体管的CD的方法和装置。 通过在硬掩模层中形成具有不同量的与其相关联的间隔物材料的硬掩模线来完成不同的CD。 对应于所选择的晶体管的硬掩模线被被涂覆在硬掩模层上的抗蚀剂覆盖或未覆盖。 然后，从硬掩模线选择性地去除间隔物材料以改变硬掩模线和相关联的侧壁间隔物的宽度。 然后通过硬掩模线中的空间蚀刻栅极层以形成具有不同宽度的栅极线和目标CD。

    PLANAR CELL ON CUT USING IN-SITU POLYMER DEPOSITION AND ETCH
    63.
    发明申请
    PLANAR CELL ON CUT USING IN-SITU POLYMER DEPOSITION AND ETCH 有权
    使用现场聚合物沉积和蚀刻的切片的平面细胞

    公开(公告)号：US20110195578A1

    公开(公告)日：2011-08-11

    申请号：US12703586

    申请日：2010-02-10

    申请人： Angela T. Hui ,  Gang Xue

    发明人： Angela T. Hui ,  Gang Xue

    IPC分类号： H01L21/3065

    CPC分类号： H01L27/11568 ,  H01L27/11565

    摘要： A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is over the shallow trench. Etching is performed on the polymer layer to expose the first region of the ONO layer, leaving the second region of the ONO unexposed. The etching continues to occur to etch the exposed ONO at the first region so that the ONO layer is etched away in the first region and the second region remains unexposed.

    摘要翻译： 提供了一种电荷存储层分离的方法和制造方法。 诸如聚合物层的层沉积在ONO层的顶部上，使得聚合物层被平坦化或近似平坦化。 ONO包括至少第一区域和第二区域，其中第一区域高于第二区域。 例如，第一区域可以是在源极/漏极区域上的ONO的部分，并且第二区域可以是在浅沟槽上的ONO的部分。 在聚合物层上进行蚀刻以暴露ONO层的第一区域，留下ONO的第二区域未曝光。 蚀刻继续发生以蚀刻在第一区域处的暴露的ONO，使得ONO层在第一区域被蚀刻掉，并且第二区域保持未曝光。

    Optical technique to detect etch process termination
    66.
    发明授权
    Optical technique to detect etch process termination 有权
    检测蚀刻工艺终止的光学技术

    公开(公告)号：US06501555B1

    公开(公告)日：2002-12-31

    申请号：US09773954

    申请日：2001-02-01

    申请人： Kouros Ghandehari ,  Bhanwar Singh ,  Angela T. Hui

    发明人： Kouros Ghandehari ,  Bhanwar Singh ,  Angela T. Hui

    IPC分类号： G01B1128

    CPC分类号： H01L22/26 ,  H01L22/12

    摘要： The disclosure describes an exemplary method of detecting a process end point during etching in the fabrication of an integrated circuit. This method can include receiving a reference signal indicative of an intensity of a light source, collecting a reflection signal reflected off a surface of an integrated circuit wafer, and comparing the reference signal and the reflection signal to locate absorption bands, the absorption band being indicative of a process end point.

    摘要翻译： 本公开描述了在集成电路的制造中在蚀刻期间检测处理终点的示例性方法。 该方法可以包括接收指示光源强度的参考信号，收集从集成电路晶片的表面反射的反射信号，以及比较参考信号和反射信号以定位吸收带，吸收带指示 的过程终点。

    Method for forming high quality multiple thickness oxide using high temperature descum
    67.
    发明授权
    Method for forming high quality multiple thickness oxide using high temperature descum 失效
    使用高温除垢法形成高品质多层氧化物的方法

    公开(公告)号：US06479411B1

    公开(公告)日：2002-11-12

    申请号：US09532347

    申请日：2000-03-21

    申请人： Angela T. Hui ,  Jusuke Ogura

    发明人： Angela T. Hui ,  Jusuke Ogura

    IPC分类号： H01L21311

    CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31662 ,  Y10S438/906 ,  Y10S438/942 ,  Y10S438/948

    摘要： A method for forming high quality multiple thickness oxide layers having different thicknesses by eliminating descum induced defects. The method includes forming an oxide layer, masking the oxide layer with a photoresist layer, and developing the photoresist layer to expose at least one region of the oxide layer. The substrate is then heated and descummed to remove any residue resulting from developing the photoresist. Alternatively, the photoresist layer may be cured prior to heating and descumming the substrate. The oxide layer is then etched, and the remaining photoresist is stripped before another layer of oxide is grown on the substrate.

    摘要翻译： 一种用于通过消除除去所引起的缺陷来形成具有不同厚度的高质量多层氧化物层的方法。 该方法包括形成氧化物层，用光致抗蚀剂层掩蔽氧化物层，以及显影光致抗蚀剂层以暴露氧化物层的至少一个区域。 然后将基材加热除去以除去由显影光致抗蚀剂产生的残留物。 或者，光致抗蚀剂层可以在加热和除去基板之前固化。 然后蚀刻氧化物层，并且在衬底上生长另一层氧化物之前剥离剩余的光致抗蚀剂。

    Method and system for providing contacts with greater tolerance for misalignment in a flash memory
    69.
    发明授权
    Method and system for providing contacts with greater tolerance for misalignment in a flash memory 有权
    用于提供触点的方法和系统，其具有对于闪存中未对准的更大容限

    公开(公告)号：US06445051B1

    公开(公告)日：2002-09-03

    申请号：US09563797

    申请日：2000-05-02

    申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko ,  John Jianshi Wang ,  Michael K. Templeton ,  Lu You ,  Angela T. Hui

    发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko ,  John Jianshi Wang ,  Michael K. Templeton ,  Lu You ,  Angela T. Hui

    IPC分类号： H01L2976

    CPC分类号： H01L21/76897 ,  H01L21/28273

    摘要： A method and system for providing a plurality of contacts in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and a plurality of field insulating regions adjacent to a portion of the plurality of gate stacks. The method and system include providing an etch stop layer covering the plurality of field insulating regions. The etch stop layer has an etch selectivity different from a field insulating region etch selectivity of the plurality of field insulating regions. The method and system also include providing an insulating layer covering the plurality of gate stacks, the plurality of field insulating regions and the etch stop layer. The method and system further include etching the insulating layer to provide a plurality of contact holes. The insulating layer etching step uses the etch stop layer to ensure that the insulating etching step does not etch through the plurality of field insulating regions. The method and system also include filling the plurality of contact holes with a conductor.

    摘要翻译： 公开了一种用于在闪速存储器件中提供多个触点的方法和系统。 闪存器件包括多个栅极堆叠和与多个栅极堆叠的一部分相邻的多个场绝缘区域。 该方法和系统包括提供覆盖多个场绝缘区域的蚀刻停止层。 蚀刻停止层具有与多个场绝缘区域的场绝缘区蚀刻选择性不同的蚀刻选择性。 该方法和系统还包括提供覆盖多个栅极叠层，多个场绝缘区域和蚀刻停止层的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供多个接触孔。 绝缘层蚀刻步骤使用蚀刻停止层来确保绝缘蚀刻步骤​​不会蚀刻穿过多个场绝缘区域。 该方法和系统还包括用导体填充多个接触孔。

    Dual bit isolation scheme for flash memory devices having polysilicon floating gates
    70.
    发明授权
    Dual bit isolation scheme for flash memory devices having polysilicon floating gates 有权
    具有多晶硅浮动栅极的闪存器件的双位隔离方案

    公开(公告)号：US06242306B1

    公开(公告)日：2001-06-05

    申请号：US09627565

    申请日：2000-07-28

    申请人： Tuan Pham ,  Angela T. Hui

    发明人： Tuan Pham ,  Angela T. Hui

    IPC分类号： H01L218247

    CPC分类号： H01L27/11519 ,  G11C16/0458 ,  H01L27/11521

    摘要： The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates. Processes for making the memory device according to the invention are also disclosed.

    摘要翻译： 本发明一般涉及半导体存储器件，更具体地说涉及在浮置栅极内采用电荷俘获来表示0或1位状态的多位闪存电可擦除可编程只读存储器（EEPROM）器件。 根据本发明的一个方面，提供一种存储器件，其包括具有双重多晶硅浮动栅极的浮动栅极晶体管，在浮置栅极之间具有隔离开口。 还公开了用于制造根据本发明的存储器件的工艺。