公开(公告)号：US07750388B2

公开(公告)日：2010-07-06

申请号：US11961076

申请日：2007-12-20

申请人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

发明人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

IPC分类号： H01L31/062 ,  H01L29/94 ,  G06F9/45

CPC分类号： H01L28/91 ,  H01L27/10861

摘要： The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET), and a design structure including the semiconductor device embodied in a machine readable medium. The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.

摘要翻译： 本发明涉及一种包含沟槽金属 - 绝缘体金属（MIM）电容器和场效应晶体管（FET）的半导体器件，以及包括体现在机器可读介质中的半导体器件的设计结构。 沟槽MIM电容器包括位于衬底中的沟槽的内壁上方的第一金属电极层，位于第一金属电极层上的沟槽中的电介质层和位于电介质层上的沟槽中的第二金属电极层。 FET包括源极区域，漏极区域，源极和漏极区域之间的沟道区域以及沟道区域上的栅极电极。 沟槽MIM电容器通过金属带连接到FET。 本发明的半导体器件可以通过在FET源极/漏极区域之后但FET源极/漏极金属硅化物接触之前形成沟槽MIM电容器以最小化FET中的金属污染的工艺来制造。

公开(公告)号：US07724707B2

公开(公告)日：2010-05-25

申请号：US11768215

申请日：2007-06-26

申请人： Gerard T. Foster ,  Subramanian S. Iyer ,  Brian J. Moore

发明人： Gerard T. Foster ,  Subramanian S. Iyer ,  Brian J. Moore

IPC分类号： H04W4/00 ,  H04W36/00

CPC分类号： H04W36/0033 ,  H04W8/26 ,  H04W16/32 ,  H04W80/04 ,  H04W88/182

摘要： A network for a cellular communication system comprises access points (105-109) supporting cells within a region (113). Each access point (105-109) has an individual proxy address of a proxy address space which is a local address space of an address proxy (101) and a common network address of a network address space which is a network wide address space. A gateway access point (103) covers an entry point to the region (113) and detects a remote station entering the region. It then determines an access point (105) in the region to which the remote station is handed over and transmits a binding message to the address proxy (101) with an indication of the access point (105). In response to receiving the binding message, the address proxy (101) establishes a binding between the common network address and the proxy address of the access point (105). Data for the remote station is then forwarded to the access point (105) using the binding.

摘要翻译： 用于蜂窝通信系统的网络包括支持区域（113）内的小区的接入点（105-109）。 每个接入点（105-109）具有作为地址代理（101）的本地地址空间的代理地址空间的单独代理地址和作为网络广域地址空间的网络地址空间的公共网络地址。 网关接入点（103）覆盖到该区域（113）的入口点并检测进入该区域的远程站。 然后，确定远程站切换到的区域中的接入点（105），并用接入点（105）的指示向地址代理（101）发送绑定消息。 响应于接收到绑定消息，地址代理（101）建立公共网络地址与接入点（105）的代理地址之间的绑定。 然后使用绑定将远程站的数据转发到接入点（105）。

公开(公告)号：US20090003263A1

公开(公告)日：2009-01-01

申请号：US11768215

申请日：2007-06-26

申请人： Gerard T. Foster ,  Subramanian S. Iyer ,  Brian J. Moore

发明人： Gerard T. Foster ,  Subramanian S. Iyer ,  Brian J. Moore

IPC分类号： H04Q7/00 ,  H04Q7/20

CPC分类号： H04W36/0033 ,  H04W8/26 ,  H04W16/32 ,  H04W80/04 ,  H04W88/182

摘要： A network for a cellular communication system comprises access points (105-109) supporting cells within a region (113). Each access point (105-109) has an individual proxy address of a proxy address space which is a local address space of an address proxy (101) and a common network address of a network address space which is a network wide address space. A gateway access point (103) covers an entry point to the region (113) and detects a remote station entering the region. It then determines an access point (105) in the region to which the remote station is handed over and transmits a binding message to the address proxy (101) with an indication of the access point (105). In response to receiving the binding message, the address proxy (101) establishes a binding between the common network address and the proxy address of the access point (105). Data for the remote station is then forwarded to the access point (105) using the binding.

摘要翻译： 用于蜂窝通信系统的网络包括支持区域（113）内的小区的接入点（105-109）。 每个接入点（105-109）具有作为地址代理（101）的本地地址空间的代理地址空间的单独代理地址和作为网络广域地址空间的网络地址空间的公共网络地址。 网关接入点（103）覆盖到该区域（113）的入口点并检测进入该区域的远程站。 然后，确定远程站切换到的区域中的接入点（105），并用接入点（105）的指示向地址代理（101）发送绑定消息。 响应于接收到绑定消息，地址代理（101）建立公共网络地址与接入点（105）的代理地址之间的绑定。 然后使用绑定将远程站的数据转发到接入点（105）。

公开(公告)号：US20080285335A1

公开(公告)日：2008-11-20

申请号：US12127909

申请日：2008-05-28

申请人： Bruce G. Elmegreen ,  Subramanian S. Iyer ,  Deok-Kee Kim ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Byeongju Park

发明人： Bruce G. Elmegreen ,  Subramanian S. Iyer ,  Deok-Kee Kim ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Byeongju Park

IPC分类号： G11C11/00

CPC分类号： H01L27/2436 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/008 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

摘要： A programmable phase change material (PCM) structure includes a heater element formed at a transistor gate level of a semiconductor device, the heater element further including a pair of electrodes connected by a thin wire structure with respect to the electrodes, the heater element configured to receive programming current passed therethrough, a layer of phase change material disposed on top of a portion of the thin wire structure, and sensing circuitry configured to sense the resistance of the phase change material.

摘要翻译： 可编程相变材料（PCM）结构包括形成在半导体器件的晶体管栅极级处的加热器元件，所述加热器元件还包括通过细线结构相对于电极连接的一对电极，所述加热器元件被配置为 接收通过其中的编程电流，设置在细线结构的一部分顶部的相变材料层以及被配置为感测相变材料的电阻的感测电路。

公开(公告)号：US07391097B2

公开(公告)日：2008-06-24

申请号：US11160151

申请日：2005-06-10

申请人： Chandrasekharan Kothandaraman ,  Subramanian S. Iyer

发明人： Chandrasekharan Kothandaraman ,  Subramanian S. Iyer

IPC分类号： H01L29/06

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides electrically-programmable fuse structures having radiation inhibitive properties for preventing non-destructive security breaches by radiation imaging techniques such as X-ray imaging, without adversely effecting fuse programmability, and methods of designing the same.

摘要翻译： 本发明提供了具有辐射抑制特性的电可编程熔丝结构，用于通过诸如X射线成像的放射线成像技术来防止非破坏性的安全漏洞，而不会对保险丝可编程性产生不利影响，以及设计熔丝可编程性的方法。

公开(公告)号：US07388244B2

公开(公告)日：2008-06-17

申请号：US11162776

申请日：2005-09-22

申请人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

发明人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L28/91 ,  H01L21/84 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1203

摘要： The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET). The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.

摘要翻译： 本发明涉及一种包含沟槽金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）的半导体器件。 沟槽MIM电容器包括位于衬底中的沟槽的内壁上方的第一金属电极层，位于第一金属电极层上的沟槽中的电介质层和位于电介质层上的沟槽中的第二金属电极层。 FET包括源极区域，漏极区域，源极和漏极区域之间的沟道区域以及沟道区域上的栅极电极。 沟槽MIM电容器通过金属带连接到FET。 本发明的半导体器件可以通过在FET源极/漏极区域之后但FET源极/漏极金属硅化物接触之前形成沟槽MIM电容器以最小化FET中的金属污染的工艺来制造。

公开(公告)号：US06821857B1

公开(公告)日：2004-11-23

申请号：US10458413

申请日：2003-06-10

申请人： Babar A. Khan ,  Rama Divakaruni ,  Subramanian S. Iyer ,  Tzyy-Ming Cheng

发明人： Babar A. Khan ,  Rama Divakaruni ,  Subramanian S. Iyer ,  Tzyy-Ming Cheng

IPC分类号： H01L21336

CPC分类号： H01L27/10873 ,  H01L21/26586 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/11 ,  H01L27/11521

摘要： A method for enhancing the on-current carrying capability of a MOSFET device is disclosed. In an explanary embodiment, the method includes recessing fill material formed within a shallow trench isolation (STI) adjacent the MOSFET so as to expose a desired depth of a sidewall of the STI, thereby increasing the effective size of a parasitic corner device of the MOSFET. The threshold voltage of the parasitic corner device is then adjusted so as to substantially equivalent to the threshold voltage of the MOSFET device.

摘要翻译： 公开了一种用于增强MOSFET器件的导通载流能力的方法。 在说明性实施例中，该方法包括在与MOSFET附近形成的浅沟槽隔离（STI）内形成凹陷填充材料，以暴露STI的侧壁的期望深度，从而增加MOSFET的寄生角装置的有效尺寸 。 然后调整寄生角装置的阈值电压，使其基本上等于MOSFET器件的阈值电压。

公开(公告)号：US5563428A

公开(公告)日：1996-10-08

申请号：US380782

申请日：1995-01-30

申请人： Bruce A. Ek ,  Stephen M. Gates ,  Fernando J. Guarin ,  Subramanian S. Iyer ,  Adrian R. Powell

发明人： Bruce A. Ek ,  Stephen M. Gates ,  Fernando J. Guarin ,  Subramanian S. Iyer ,  Adrian R. Powell

IPC分类号： H01L21/02 ,  H01L21/04 ,  H01L21/20 ,  H01L27/12 ,  H01L31/10 ,  H01L31/18 ,  H01L33/00 ,  H01S5/00 ,  H01S5/323 ,  H01L31/0312 ,  H01L27/108 ,  H01L31/0328

CPC分类号： H01L33/007 ,  H01L21/0445 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A structure is fabricated comprising a substrate, a dielectric layer formed over the substrate, and a single crystal layer of a compound formed over the dielectric layer. The single crystal layer is formed by the chemical reaction of at least a first element with an initial single crystal layer of a second element on the dielectric layer having an initial thickness of about 100 to about 10,000 angstroms.According to another aspect, a carbide single crystal layer is provided on a substrate by depositing carbon from a solid carbon source at a low rate and low temperature, followed by reacting the carbon with the underlying layer to convert it to the carbide.

摘要翻译： 制造的结构包括衬底，在衬底上形成的电介质层和在电介质层上形成的化合物的单晶层。 单晶层通过至少第一元素与电介质层上初始厚度为约100至约10,000埃的第二元素的初始单晶层的化学反应形成。 根据另一方面，通过在低速率和低温下从固体碳源沉积碳，然后使碳与下层反应以将其转化为碳化物，在基板上提供碳化物单晶层。

公开(公告)号：US5494849A

公开(公告)日：1996-02-27

申请号：US409208

申请日：1995-03-23

申请人： Subramanian S. Iyer ,  Emil Baran ,  Mark L. Mastroianni ,  Robert A. Craven

发明人： Subramanian S. Iyer ,  Emil Baran ,  Mark L. Mastroianni ,  Robert A. Craven

IPC分类号： H01L21/322 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/3226 ,  H01L21/76251 ,  Y10S148/012 ,  Y10S148/135

摘要： A single-etch stop process for the manufacture of silicon-on-insulator substrates. The process includes forming a silicon-on-insulator bonded substrate comprising a handle wafer, a device wafer, a device layer having a thickness of between about 0.5 and 50 micrometers, and an oxide layer with the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the handle wafer, the device wafer having a boron concentration of at least about 1.times.10.sup.18 boron atoms/cm.sup.3 and a resistivity of about 0.01 to about 0.02 ohm-cm. A portion of the device wafer is mechanically removed from the silicon-on-insulator bonded substrate wherein the device wafer has a total thickness variation across the surface of the wafer of less than about 2 micrometers and a defect-free surface after the mechanical removal step. The defect-free surface of the device wafer is thereafter etched away to expose the device layer, and the exposed device layer is polished to produce a silicon-on-insulator substrate having a device layer the total thickness variation of which does not exceed 10% of the maximum thickness of the device layer.

摘要翻译： 用于制造绝缘体上硅衬底的单蚀刻停止工艺。 该方法包括形成绝缘体上硅键合衬底，其包括处理晶片，器件晶片，厚度在约0.5微米至50微米之间的器件层，以及具有器件层位于器件晶片和晶体管之间的氧化物层 氧化物层和位于器件层和处理晶片之间的氧化物层，器件晶片的硼浓度为至少约1×1018硼原子/ cm3，电阻率为约0.01至约0.02欧姆 - 厘米。 将器件晶片的一部分从绝缘体上硅键合衬底机械地移除，其中器件晶片具有小于约2微米的整个晶片表面的总厚度变化，以及机械去除步骤之后的无缺陷表面 。 此后，将器件晶片的无缺陷表面蚀刻掉以暴露器件层，并且对裸露的器件层进行抛光以产生绝缘体上硅衬底，其具有总厚度变化不超过10％的器件层 的器件层的最大厚度。

公开(公告)号：US5463254A

公开(公告)日：1995-10-31

申请号：US279669

申请日：1994-07-25

申请人： Subramanian S. Iyer ,  Richard D. Thompson ,  King-Ning Tu

发明人： Subramanian S. Iyer ,  Richard D. Thompson ,  King-Ning Tu

IPC分类号： H01L21/20 ,  H01L21/3205 ,  H01L21/74 ,  H01L23/52 ,  H01L23/535 ,  H01L21/283 ,  H01L23/48

CPC分类号： H01L21/743 ,  H01L23/535 ,  H01L2924/0002

摘要： An epitaxial conductor and a method for forming buried conductor patterns is described incorporating a layer of single crystalline silicon, a pattern formed therein such as a trench, a layer of metal silicide epitaxial formed on the bottom surface of the pattern or trench, a layer of silicon epitaxially formed thereover, and a layer of metal silicide epitaxially formed over the silicon layer. The invention overcomes the problem of twinning defects in the top surface of epitaxial silicide layers.

摘要翻译： 描述了外延导体和形成掩埋导体图案的方法，其结合了单晶硅层，形成在其中的图案，例如沟槽，形成在图案或沟槽的底表面上的金属硅化物层，一层 在其上外延形成的硅，以及在硅层上外延形成的金属硅化物层。 本发明克服了外延硅化物层的上表面的孪晶缺陷的问题。