利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

46 条记录 (耗时 0.022 秒)

    Trench metal-insulator metal (MIM) capacitors
    1.
    发明授权
    Trench metal-insulator metal (MIM) capacitors 失效
    沟槽金属绝缘体金属（MIM）电容器

    公开(公告)号：US07750388B2

    公开(公告)日：2010-07-06

    申请号：US11961076

    申请日：2007-12-20

    申请人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

    发明人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

    IPC分类号： H01L31/062 ,  H01L29/94 ,  G06F9/45

    CPC分类号： H01L28/91 ,  H01L27/10861

    摘要： The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET), and a design structure including the semiconductor device embodied in a machine readable medium. The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.

    摘要翻译： 本发明涉及一种包含沟槽金属 - 绝缘体金属（MIM）电容器和场效应晶体管（FET）的半导体器件，以及包括体现在机器可读介质中的半导体器件的设计结构。 沟槽MIM电容器包括位于衬底中的沟槽的内壁上方的第一金属电极层，位于第一金属电极层上的沟槽中的电介质层和位于电介质层上的沟槽中的第二金属电极层。 FET包括源极区域，漏极区域，源极和漏极区域之间的沟道区域以及沟道区域上的栅极电极。 沟槽MIM电容器通过金属带连接到FET。 本发明的半导体器件可以通过在FET源极/漏极区域之后但FET源极/漏极金属硅化物接触之前形成沟槽MIM电容器以最小化FET中的金属污染的工艺来制造。

    Trench metal-insulator-metal (MIM) capacitors and method of fabricating same
    2.
    发明授权
    Trench metal-insulator-metal (MIM) capacitors and method of fabricating same 有权
    沟槽金属 - 绝缘体金属（MIM）电容器及其制造方法

    公开(公告)号：US07388244B2

    公开(公告)日：2008-06-17

    申请号：US11162776

    申请日：2005-09-22

    申请人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

    发明人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L28/91 ,  H01L21/84 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1203

    摘要： The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET). The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.

    摘要翻译： 本发明涉及一种包含沟槽金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）的半导体器件。 沟槽MIM电容器包括位于衬底中的沟槽的内壁上方的第一金属电极层，位于第一金属电极层上的沟槽中的电介质层和位于电介质层上的沟槽中的第二金属电极层。 FET包括源极区域，漏极区域，源极和漏极区域之间的沟道区域以及沟道区域上的栅极电极。 沟槽MIM电容器通过金属带连接到FET。 本发明的半导体器件可以通过在FET源极/漏极区域之后但FET源极/漏极金属硅化物接触之前形成沟槽MIM电容器以最小化FET中的金属污染的工艺来制造。

    TRENCH METAL-INSULATOR METAL (MIM) CAPACITORS
    3.
    发明申请
    TRENCH METAL-INSULATOR METAL (MIM) CAPACITORS 失效
    金属绝缘子金属（MIM）电容器

    公开(公告)号：US20090159948A1

    公开(公告)日：2009-06-25

    申请号：US11961076

    申请日：2007-12-20

    申请人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

    发明人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

    IPC分类号： H01L27/108

    CPC分类号： H01L28/91 ,  H01L27/10861

    摘要： The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET), and a design structure including the semiconductor device embodied in a machine readable medium. The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.

    摘要翻译： 本发明涉及一种包含沟槽金属 - 绝缘体金属（MIM）电容器和场效应晶体管（FET）的半导体器件，以及包括体现在机器可读介质中的半导体器件的设计结构。 沟槽MIM电容器包括位于衬底中的沟槽的内壁上方的第一金属电极层，位于第一金属电极层上的沟槽中的电介质层和位于电介质层上的沟槽中的第二金属电极层。 FET包括源极区域，漏极区域，源极和漏极区域之间的沟道区域以及沟道区域上的栅极电极。 沟槽MIM电容器通过金属带连接到FET。 本发明的半导体器件可以通过在FET源极/漏极区域之后但FET源极/漏极金属硅化物接触之前形成沟槽MIM电容器以最小化FET中的金属污染的工艺来制造。

    Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same
    4.
    发明授权
    Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same 有权
    与中间线金属触点集成的沟槽金属 - 绝缘体金属（MIM）电容器及其制造方法

    公开(公告)号：US07276751B2

    公开(公告)日：2007-10-02

    申请号：US11162413

    申请日：2005-09-09

    申请人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

    发明人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

    IPC分类号： H01L29/76

    CPC分类号： H01L27/10861 ,  H01L28/91 ,  H01L29/945

    摘要： The present invention relates to a semiconductor device that contains at least one trench metal-oxide-metal (MIM) capacitor and at least one other logic circuitry component, preferably at least one field effect transistor (FET). The trench MIM capacitor is located in a trench in a substrate and comprises inner and outer metallic electrode layers with a dielectric layer therebetween. The FET comprises a source region, a drain region, a channel region, and at least one metal contact connected with the source or drain region. The present invention also relates to a fabrication process, which integrates the processing steps for fabricating the trench MIM capacitor with the conventional middle-of-line processing steps for fabricating metal contacts, so that the inner metallic electrode layer of the trench MIM capacitor and the metal contact of the FET or other logic circuitry components are formed by a single middle-of-line processing step and comprise essentially the same metallic material.

    摘要翻译： 本发明涉及一种半导体器件，其包含至少一个沟槽金属氧化物金属（MIM）电容器和至少一个其它逻辑电路部件，优选至少一个场效应晶体管（FET）。 沟槽MIM电容器位于衬底中的沟槽中，并且包括其间具有介电层的内部和外部金属电极层。 FET包括源极区，漏极区，沟道区以及与源极或漏极区连接的至少一个金属接触。 本发明还涉及一种制造工艺，其将用于制造沟槽MIM电容器的处理步骤与用于制造金属触点的常规中间线处理步骤相结合，使得沟槽MIM电容器的内部金属电极层和 FET或其他逻辑电路部件的金属接触通过单个中间线处理步骤形成并且包括基本上相同的金属材料。

    Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits
    5.
    发明授权
    Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits 有权
    减小半导体集成电路中寄生电容的结构和方法

    公开(公告)号：US07825019B2

    公开(公告)日：2010-11-02

    申请号：US11863724

    申请日：2007-09-28

    申请人： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Vidhya Ramachandran

    发明人： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Vidhya Ramachandran

    IPC分类号： H01L21/44

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/522 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/926 ,  Y10S438/928 ,  H01L2924/00

    摘要： A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.

    摘要翻译： 半导体结构及其形成方法。 该结构包括（a）包括半导体器件的衬底和（b）在衬底顶部上的第一ILD（层间电介质）层。 该结构还包括第一ILD层中的N个第一实际金属线，N是正整数。 N个第一实际金属线电连接到半导体器件。 该结构还包括第一ILD层中的第一沟槽。 第一条沟没有完全填满固体材料。 如果第一沟槽被完全填充第一虚拟金属线，则（i）第一虚设金属线不与任何半导体器件电连接，并且（ii）N个第一实际金属线和第一虚拟金属线提供基本均匀的 跨越第一ILD层的金属线的图案密度。

    TRENCH METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHOD OF FABRICATING SAME
    8.
    发明申请
    TRENCH METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHOD OF FABRICATING SAME 有权
    金属绝缘子金属（MIM）电容器及其制造方法

    公开(公告)号：US20070063244A1

    公开(公告)日：2007-03-22

    申请号：US11162776

    申请日：2005-09-22

    申请人： Herbert Ho ,  Subramanian Iyer ,  Vidhya Ramachandran

    发明人： Herbert Ho ,  Subramanian Iyer ,  Vidhya Ramachandran

    IPC分类号： H01L21/8242 ,  H01L29/94

    CPC分类号： H01L28/91 ,  H01L21/84 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1203

    摘要： The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET). The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.

    摘要翻译： 本发明涉及一种包含沟槽金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）的半导体器件。 沟槽MIM电容器包括位于衬底中的沟槽的内壁上方的第一金属电极层，位于第一金属电极层上的沟槽中的电介质层和位于电介质层上的沟槽中的第二金属电极层。 FET包括源极区域，漏极区域，源极和漏极区域之间的沟道区域以及沟道区域上的栅极电极。 沟槽MIM电容器通过金属带连接到FET。 本发明的半导体器件可以通过在FET源极/漏极区域之后但FET源极/漏极金属硅化物接触之前形成沟槽MIM电容器以最小化FET中的金属污染的工艺来制造。

    LOW-K DIELECTRIC PROTECTION SPACER FOR PATTERNING THROUGH SUBSTRATE VIAS THROUGH A LOW-K WIRING LAYER
    9.
    发明申请
    LOW-K DIELECTRIC PROTECTION SPACER FOR PATTERNING THROUGH SUBSTRATE VIAS THROUGH A LOW-K WIRING LAYER 有权
    低K电介质保护间隔板，用于通过低K布线层通过基板VIAS

    公开(公告)号：US20130113068A1

    公开(公告)日：2013-05-09

    申请号：US13588438

    申请日：2012-08-17

    申请人： Vidhya Ramachandran ,  Shiqun Gu

    发明人： Vidhya Ramachandran ,  Shiqun Gu

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A low-K value dielectric protection spacer for patterning through substrate vias (TSVs) through a low-K value wiring layer. A method for forming a low-K value dielectric protection spacer includes etching a via opening through a low-K value dielectric interconnect layer. A protective layer is deposited in the via opening and on the low-K value dielectric interconnect layer. At least a portion of the protective layer is etched from the bottom of the via opening and from a horizontal surface of the low-K value dielectric interconnect layer. The etching leaving a protective sidewall spacer on a sidewall of the via opening. A through substrate via is etched through the bottom of the via opening and through the semiconductor substrate. The through substrate via is filled with a conductive material.

    摘要翻译： 低K值介电保护间隔物，用于通过低K值布线层通过衬底通孔（TSV）进行构图。 形成低K值介电保护间隔物的方法包括通过低K值电介质互连层蚀刻通孔。 保护层沉积在通孔开口和低K值电介质互连层上。 保护层的至少一部分从通孔开口的底部和低K值电介质互连层的水平表面被蚀刻。 蚀刻在通孔开口的侧壁上留下保护性侧壁间隔物。 穿通基板通孔被蚀刻穿过通孔开口的底部并穿过半导体基板。 直通基板通孔用导电材料填充。