摘要:
A method is provided for depositing aluminum thin film layers to form improved quality contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.
摘要:
A method for forming a thin oxide layer structure includes the step of first growing a dry oxide layer. A layer grown in steam and chlorine is formed next, followed by a final dry oxide layer. An anneal step in an inert gas further improves the quality of the oxide layer. The structure formed by such a process provides a layer of steam grown oxide sandwiched between two layers of oxide grown in a dry atmosphere.
摘要:
A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the first metal silicide layer from damage.
摘要:
The method for producing the surface reflectance of the metal layer during semiconductor processing includes the step of roughening the surface of a metal layer prior to forming the photoresist thereon. The roughened surface reduces reflections that can cause metal notching effects. The step of roughening the surface includes depositing a layer (34) of aluminum which is substantially thinner than the thickness of the primary metal layer by a sputtering process.
摘要:
A process for forming a capping layer over a titanium silicide layer includes forming a layer of polysilicon (16) over a gate-oxide layer (14). A layer of titanium (18) is then formed over the poly layer (16) followed by deposition of a composite layer of tantalum silicide (20). The structure is then patterned and subjected to an annealing process to form a titanium silicide layer (22) covered by the capping layer (20) of tantalum silicide. The tantalum silicide provides a much higher oxidation resistant layer with the underlying titanium silicide providing the desirable conductive properties needed for long runs of interconnects on a semiconductor structure.
摘要:
A method for making a CMOS integrated circuit device saves on masking steps by using unmasked blanket implantations at various steps of the process, such as setting the threshold voltages of the transistors, forming a lightly doped drain for the N-channel transistor, and for forming the source/drain regions of the N-type transistor.