公开(公告)号：US06669787B2

公开(公告)日：2003-12-30

申请号：US09878980

申请日：2001-06-12

Applicant: Murray Fulton Gillies ,  Antonius Emilius Theodorus Kuiper

Inventor： Murray Fulton Gillies ,  Antonius Emilius Theodorus Kuiper

IPC: C23C880

CPC classification number: H01L27/224 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  G11B5/3903 ,  G11B5/3925 ,  H01F10/3259 ,  H01F10/3268 ,  H01F41/307 ,  H01L43/12 ,  Y10S148/118 ,  Y10T428/1129

Abstract: The invention relates to a method of manufacturing a spin valve structure (1) of the GMR-type. Such a structure includes a stack of a magnetic layer (11a 11b), a nonmagnetic layer (15) and a sense layer (17) of a ferromagnetic material. In order to obtain a spin valve structure having a very good GMR effect the method comprises the following specific steps: oxidation of the ferromagnetic material of the sense layer; deposition of aluminium on the oxidized ferromagnetic material; oxidation of the deposited aluminium using oxygen from the oxidized ferromagnetic material.

公开(公告)号：US06355580B1

公开(公告)日：2002-03-12

申请号：US09146710

申请日：1998-09-03

Applicant: Li Li ,  Pai-Hung Pan

Inventor： Li Li ,  Pai-Hung Pan

IPC: H01L2131

CPC classification number: H01L21/28008 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02351 ,  H01L21/26506 ,  H01L21/31662 ,  H01L21/76213 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/42368 ,  H01L29/66575 ,  Y10S148/116 ,  Y10S148/118

Abstract: Oxidation methods and resulting structures comprising providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.

公开(公告)号：US5912486A

公开(公告)日：1999-06-15

申请号：US842863

申请日：1997-04-17

Applicant: Scott R. Summerfelt

Inventor： Scott R. Summerfelt

IPC: C23C14/08 ,  H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/51 ,  H05K1/03

CPC classification number: H01L21/28185 ,  H01L21/02197 ,  H01L21/02304 ,  H01L21/28158 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/314 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  Y10S148/014 ,  Y10S148/118 ,  Y10S438/967

Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a buffer layer of non-Pb/Bi-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate; and depositing a Pb/Bi-containing high-dielectric constant oxide on the buffer layer. Alternately this may be a structure useful in semiconductor circuitry, comprising: a buffer layer 26 of non-lead-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate 10; and a lead-containing high-dielectric constant oxide 28 on the buffer layer. Preferably a germanium layer 12 is epitaxially grown on the semiconductor substrate and the buffer layer is grown on the germanium layer. When the substrate is silicon, the non-Pb/Bi-containing high-dielectric constant oxide layer is preferably less than about 10 nm thick. A second non-Pb/Bi-containing high-dielectric constant oxide layer 30 may be grown on top of the Pb/Bi-containing high-dielectric constant oxide and a conducting layer (top electrode 32) may also be grown on the second non-Pb/Bi-containing high-dielectric constant oxide layer.

Abstract translation: 这是用于制造在半导体电路中有用的结构的方法。 该方法包括：在半导体衬底上直接或间接生长非Pb / Bi的高介电常数氧化物层的缓冲层; 以及在所述缓冲层上沉积含Pb / Bi的高介电常数氧化物。 或者，这可以是在半导体电路中有用的结构，其包括：直接或间接地在半导体衬底10上的非含铅高介电常数氧化物层的缓冲层26; 和在缓冲层上的含铅高介电常数氧化物28。 优选地，在半导体衬底上外延生长锗层12，并且在锗层上生长缓冲层。 当衬底是硅时，非Pb / Bi的高介电常数氧化物层的厚度优选小于约10nm。 可以在含Pb / Bi的高介电常数氧化物的顶部上生长第二非Pb / Bi的高介电常数氧化物层30，并且还可以在第二非绝缘材料上生长导电层（顶电极32） -Pb / Bi高介电常数氧化物层。

公开(公告)号：US5747880A

公开(公告)日：1998-05-05

申请号：US751901

申请日：1996-11-18

Applicant: Robert H. Havemann ,  Shin-Puu Jeng ,  Bruce E. Gnade ,  Chih-Chen Cho

Inventor： Robert H. Havemann ,  Shin-Puu Jeng ,  Bruce E. Gnade ,  Chih-Chen Cho

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/47 ,  H01L21/471

CPC classification number: H01L21/02362 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02359 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10S148/043 ,  Y10S148/118

Abstract: This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract translation: 本发明提供了一种半导体器件及其制造方法，其显着降低了相邻导体之间的电容，以及强调机械强度，蚀刻兼容性和良好热传递的层间电介质结构。 该方法可以包括在导体24之间施加溶液，然后将溶液凝胶化，表面改性和干燥以形成极其多孔的介电层28.多孔介质层30可形成在多孔层28之上，多孔层28可以完成 层间电介质，并提供机械强度，热传递和用于通孔蚀刻的固体层。 公开了一种用于产生多孔介电层的新方法，其可以在真空或环境压力下完成，但是在干燥期间导致电介质的孔隙率，孔径和收缩相当于仅通过在超临界压力下干燥凝胶可获得的电介质层。

公开(公告)号：US5646074A

公开(公告)日：1997-07-08

申请号：US573960

申请日：1995-12-15

Applicant: Rickey Chen ,  Rex Chen

Inventor： Rickey Chen ,  Rex Chen

IPC: H01L21/28 ,  H01L21/02

CPC classification number: H01L21/28185 ,  H01L21/28211 ,  Y10S148/117 ,  Y10S148/118 ,  Y10S438/906 ,  Y10S438/974

Abstract: Disclosed is a process for manufacturing a gate oxide of a MOSFET. Since the performance of the gate oxide is deteriorated in photo resist removing, DI healing and high temperature annealing are introduced to recover the gate oxide. A process for manufacturing the gate oxide of the MOSFET on a wafer, includes the steps of: pre-cleaning the wafer, forming gate oxide layer, coating a photo resist, exposing the photo resist, developing the photo resist, implanting ions over the developed photo resist, removing the photo resist, post-cleaning the gate oxide for the purpose of good attachment of a gate polysilicon layer, DI healing the gate oxide, and annealing the gate oxide at a high temperature. As a result, the pass rates for Ebd and Qbd tests of the gate oxide increase.

Abstract translation: 公开了一种用于制造MOSFET的栅极氧化物的工艺。 由于栅极氧化物的性能在光致抗蚀剂去除中劣化，所以引入DI愈合和高温退火以恢复栅极氧化物。 一种用于在晶片上制造MOSFET的栅极氧化物的工艺包括以下步骤：预先清洗晶片，形成栅极氧化层，涂覆光致抗蚀剂，曝光光致抗蚀剂，显影光致抗蚀剂， 光刻胶，去除光致抗蚀剂，对栅极氧化物进行后清洗，以便良好地附着栅极多晶硅层，DI修复栅极氧化物，并在高温下退火栅极氧化物。 结果，栅极氧化物的Ebd和Qbd测试的合格率增加。

公开(公告)号：US5645943A

公开(公告)日：1997-07-08

申请号：US546192

申请日：1995-10-20

Applicant: Tadahiro Ohmi ,  Hitoshi Inaba

Inventor： Tadahiro Ohmi ,  Hitoshi Inaba

IPC: H01L21/687 ,  B32B15/04

CPC classification number: H01L21/68707 ,  Y10S148/118 ,  Y10T428/31678

Abstract: An electrified object contact material characterized in that an oxide film formed in a high purity oxidizing atmosphere with a thickness from several tens to 100 .ANG. is formed at least in a section directly contacting an electrified object. By using the contact component according to the present invention, the electric potential of a wafer can always be suppressed to 50 V or less, and moreover, contamination of a wafer (especially by a metallic material) can completely be eliminated.

Abstract translation: 一种带电的物体接触材料，其特征在于至少在直接接触带电物体的部分中形成厚度为几十至100埃的高纯度氧化气氛中的氧化膜。 通过使用本发明的接触部件，可以将晶片的电位总是抑制在50V以下，此外，可以完全消除晶片（特别是金属材料）的污染。

公开(公告)号：US5567980A

公开(公告)日：1996-10-22

申请号：US378102

申请日：1995-01-26

Applicant: Nick Holonyak, Jr. ,  John M. Dallesasse

Inventor： Nick Holonyak, Jr. ,  John M. Dallesasse

IPC: H01L21/316 ,  H01S5/20 ,  H01S5/22 ,  H01S5/40 ,  H01L27/12

CPC classification number: H01L21/31654 ,  H01S5/2059 ,  H01S5/2215 ,  H01S5/4031 ,  Y10S148/065 ,  Y10S148/116 ,  Y10S148/117 ,  Y10S148/118

Abstract: A method of forming a native oxide from an aluminum-bearing Group III-V semiconductor material is provided. The method entails exposing the aluminum-bearing Group III-V semiconductor material to a water-containing environment and a temperature of at least about 375.degree. C. to convert at least a portion of said aluminum-bearing material to a native oxide characterized in that the thickness of said native oxide is substantially the same as or less than the thickness of that portion of said aluminum-bearing Group III-V semiconductor material thus converted. The native oxide thus formed has particular utility in electrical and optoelectrical devices, such as lasers.

Abstract translation: 提供了从含铝III-V族半导体材料形成天然氧化物的方法。 该方法需要将含铝III-V族半导体材料暴露于含水环境和至少约375℃的温度，以将至少一部分所述含铝材料转化为天然氧化物，其特征在于 所述自然氧化物的厚度基本上等于或小于由此转化的所述含铝III-V族半导体材料的那部分的厚度。 如此形成的自然氧化物在诸如激光器的电和光电装置中具有特别的用途。

公开(公告)号：US5523240A

公开(公告)日：1996-06-04

申请号：US219286

申请日：1994-03-28

Applicant: Hongyong Zhang ,  Shunpei Yamazaki

Inventor： Hongyong Zhang ,  Shunpei Yamazaki

IPC: H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L29/49 ,  H01L21/225 ,  H01L21/268

CPC classification number: H01L27/1214 ,  H01L29/4908 ,  H01L29/66757 ,  Y10S148/118

Abstract: A gate-insulated thin film transistor is disclosed. One improvement is that the thin film transistor is formed on a substrate through a blocking layer in between so that it is possible to prevent the transistor from being contaminated with impurities such as alkali ions which exist in the substrate. Also, a halogen is added to either or both of the blocking layer and a gate insulator of the transistor in order that impurities such as alkaline ions, dangling bonds and the like can be neutralized, therefore, the reliability of the device is improved.

Abstract translation: 公开了一种栅极绝缘薄膜晶体管。 一个改进是薄膜晶体管通过其间的阻挡层形成在衬底上，使得可以防止晶体管被存在于衬底中的诸如碱离子的杂质污染。 此外，为阻止层和晶体管的栅极绝缘体中的任一个或两者添加卤素，以便可以中和诸如碱性离子，悬挂键等的杂质，因此提高了器件的可靠性。

公开(公告)号：US5393352A

公开(公告)日：1995-02-28

申请号：US127222

申请日：1993-09-27

Applicant: Scott R. Summerfelt

Inventor： Scott R. Summerfelt

IPC: C23C14/08 ,  H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/51 ,  H05K1/03 ,  H01L29/12

CPC classification number: H01L21/28185 ,  H01L21/02197 ,  H01L21/02304 ,  H01L21/28158 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/314 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  Y10S148/014 ,  Y10S148/118 ,  Y10S438/967

Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a buffer layer of non-Pb/Bi-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate; and depositing a Pb/Bi-containing high-dielectric constant oxide on the buffer layer. Alternately this may be a structure useful in semiconductor circuitry, comprising: a buffer layer 26 of non-lead-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate 10; and a lead-containing high-dielectric constant oxide 28 on the buffer layer. Preferably a germanium layer 12 is epitaxially grown on the semiconductor substrate and the buffer layer is grown on the germanium layer. When the substrate is silicon, the non-Pb/Bi-containing high-dielectric constant oxide layer is preferably less than about 10 nm thick. A second non-Pb/Bi-containing high-dielectric constant oxide layer 30 may be grown on top of the Pb/Bi-containing high-dielectric constant oxide and a conducting layer (top electrode 32) may also be grown on the second non-Pb/Bi-containing high-dielectric constant oxide layer.

Abstract translation: 这是用于制造在半导体电路中有用的结构的方法。 该方法包括：在半导体衬底上直接或间接生长非Pb / Bi的高介电常数氧化物层的缓冲层; 以及在所述缓冲层上沉积含Pb / Bi的高介电常数氧化物。 或者，这可以是在半导体电路中有用的结构，其包括：直接或间接地在半导体衬底10上的非含铅高介电常数氧化物层的缓冲层26; 和在缓冲层上的含铅高介电常数氧化物28。 优选地，在半导体衬底上外延生长锗层12，并且在锗层上生长缓冲层。 当衬底是硅时，非Pb / Bi的高介电常数氧化物层的厚度优选小于约10nm。 可以在含Pb / Bi的高介电常数氧化物的顶部上生长第二非Pb / Bi的高介电常数氧化物层30，并且还可以在第二非绝缘材料上生长导电层（顶电极32） -Pb / Bi高介电常数氧化物层。

公开(公告)号：US5376591A

公开(公告)日：1994-12-27

申请号：US895472

申请日：1992-06-08

Applicant: Kazuo Maeda ,  Noboru Tokumasu ,  Yuko Nishimoto

Inventor： Kazuo Maeda ,  Noboru Tokumasu ,  Yuko Nishimoto

IPC: H01L21/3105 ,  H01L21/316 ,  H01L21/02

CPC classification number: H01L21/02164 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/31662 ,  Y10S148/118

Abstract: A, method for forming semiconductor device, includes forming an insulating film on a body by chemical vapor deposition, at low temperature raising the temperature of, the body, and exposing the body to plasma gas.

Abstract translation: A，形成半导体器件的方法包括：通过化学气相沉积在体上形成绝缘膜，在低温下使身体的温度升高，并使身体暴露于等离子体气体。