公开(公告)号：US08330496B2

公开(公告)日：2012-12-11

申请号：US12620903

申请日：2009-11-18

申请人： Masanao Yamaoka ,  Takayuki Kawahara

发明人： Masanao Yamaoka ,  Takayuki Kawahara

IPC分类号： H03K19/20 ,  H03K19/094

CPC分类号： H03K19/0016 ,  G11C11/413

摘要： An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state.A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.

摘要翻译： 本发明的目的是提供一种降低驱动电路的泄漏电流的技术，该驱动电路在处于其待机状态时必须保持电位（或信息）的驱动电路。 本发明的半导体集成电路器件包括用于驱动电路块的驱动电路。 该驱动电路由具有不同栅极氧化膜厚度的栅极的双栅极晶体管构成。 当电路块处于其待机状态时，具有较薄栅极氧化膜的双栅极晶体管的栅极截止，并且具有较厚栅极氧化膜的栅极导通。 这种布置允许减少电路块和驱动电路的漏电流，同时允许驱动电路传送或切断电路块的电力。

公开(公告)号：US08184463B2

公开(公告)日：2012-05-22

申请号：US12636758

申请日：2009-12-13

申请人： Makoto Saen ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

发明人： Makoto Saen ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

IPC分类号： G11C5/06 ,  G11C7/00 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L25/0657 ,  G11C5/02 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.

摘要翻译： 通过采用其中执行一次发送的电路（TR-00T）和用于执行多个接收（TR-10R，TR-20R，TR-30R）的电路的连接拓扑结构来消除对中介操作的需要 连接到一个穿透电极组（例如，TSVGL-0）。 为了实现连接拓扑，即使在堆叠多个LSI的情况下，尤其是用于指定用于发送的各个穿透电极端口或用于接收的可编程存储器元件，以及地址分配 各个贯通电极端口安装在堆叠的LSI中。

公开(公告)号：US20100201429A1

公开(公告)日：2010-08-12

申请号：US12767548

申请日：2010-04-26

申请人： Takayuki KAWAHARA ,  Masanao Yamaoka

发明人： Takayuki KAWAHARA ,  Masanao Yamaoka

IPC分类号： H03K17/687

CPC分类号： H01L27/1203 ,  H01L29/78645 ,  H01L29/78648

摘要： The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit.In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.

摘要翻译： 本发明提供一种可在宽温度范围内工作的高速，低功耗的LSI，其具有根据电路的工作特性专门使用具有后栅的MOS晶体管。 在LSI中，使用具有嵌入的氧化膜层的FD-SOI结构，并且将埋入的氧化膜层的下半导体区域用作后栅。 在逻辑电路块中具有小负载的逻辑电路中的后门的电压响应于块外部的激活而被控制。 栅极和背栅彼此连接的晶体管用于产生背栅极驱动信号的电路，以及具有诸如电路块输出部分的重负载的逻辑电路，并且后门直接根据 到门输入信号。

公开(公告)号：US20100027322A1

公开(公告)日：2010-02-04

申请号：US12563231

申请日：2009-09-21

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/417

摘要： In this invention, high manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS•SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

摘要翻译： 在本发明中，实现了高制造成品率，并补偿了CMOS.SRAM中的每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据测定结果分别被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS.SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。

公开(公告)号：US07646662B2

公开(公告)日：2010-01-12

申请号：US12325783

申请日：2008-12-01

申请人： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

发明人： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC分类号： G11C5/14

CPC分类号： G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

摘要翻译： 系统LSI中的逻辑电路具有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。

公开(公告)号：US07498637B2

公开(公告)日：2009-03-03

申请号：US11151455

申请日：2005-06-14

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Kiyoo Itoh ,  Takayuki Kawahara

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Kiyoo Itoh ,  Takayuki Kawahara

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L27/11 ,  G11C11/00

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/108 ,  H01L27/1203 ,  Y10S257/903

摘要： A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.

摘要翻译： SRAM存储器由FD-SOI晶体管组成，通过控制构成驱动晶体管的SOI晶体管的埋入氧化膜下​​的层的电位来提高存储单元的性能。 提高了处于低功率电压状态的SRAM电路的性能。 在由FD-SOI晶体管构成的SRAM存储单元中，控制BOX层下的阱的电位来控制阈值电压Vth，从而增加电流。 因此，可以稳定存储单元的操作。

公开(公告)号：US20080316800A1

公开(公告)日：2008-12-25

申请号：US12222753

申请日：2008-08-15

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

IPC分类号： G11C11/00

CPC分类号： G11C11/417 ,  G11C5/14 ,  G11C5/148

摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。

公开(公告)号：US20080247220A1

公开(公告)日：2008-10-09

申请号：US12133343

申请日：2008-06-04

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

IPC分类号： G11C11/00

CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导被增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

公开(公告)号：US20080117692A1

公开(公告)日：2008-05-22

申请号：US12003970

申请日：2008-01-04

申请人： Masanao Yamaoka ,  Kenichi Osada

发明人： Masanao Yamaoka ,  Kenichi Osada

IPC分类号： G11C5/14

CPC分类号： G11C29/02 ,  G11C5/146 ,  G11C5/147 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

摘要： An SRAM circuit operates at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the produced transistor in the SRAM circuit is detected to compare the operating voltage of a memory cell with the operating voltage of a peripheral circuit in order to adjust it to the optimum value, and the substrate bias voltage is further controlled.

公开(公告)号：US20070297270A1

公开(公告)日：2007-12-27

申请号：US11812193

申请日：2007-06-15

申请人： Shigenobu Komatsu ,  Masanao Yamaoka

发明人： Shigenobu Komatsu ,  Masanao Yamaoka

IPC分类号： G11C8/00 ,  G11C11/00

CPC分类号： G11C8/08 ,  G11C8/18 ,  G11C11/412

摘要： The present invention provides a technique capable of achieving area reduction on a semiconductor integrated circuit device mounted with a time sharing virtual multi port memory or the like. By providing a configuration including a single port memory, data latch circuit for plural ports, a selector for selecting a port to be connected to the single port memory, a time sharing control signal generating circuit and the like, in which an operation termination signal inside the single port memory (a word line rising signal, a sense amplifier driving signal for data read or the like) is inputted to the time sharing control signal generating circuit to produce a port switching control signal and an operation control signal for the single port memory, a time sharing virtual multi port memory with a reduced area can be realized which requires no clock generating circuit for time sharing control newly.

摘要翻译： 本发明提供一种能够在安装有时间分配虚拟多端口存储器等的半导体集成电路装置上实现面积缩小的技术。 通过提供包括单端口存储器，用于多个端口的数据锁存电路，用于选择要连接到单端口存储器的端口的选择器，时间共享控制信号生成电路等，其中内部的操作终止信号 将单端口存储器（字线上升信号，用于数据读取的读出放大器驱动信号等）输入到时间共享控制信号发生电路，以产生用于单端口存储器的端口切换控制信号和操作控制信号 可以实现具有减小面积的虚拟多端口存储器的时间分配，这不需要新的时间分配控制的时钟发生电路。