公开(公告)号：US08633071B2

公开(公告)日：2014-01-21

申请号：US13278667

申请日：2011-10-21

申请人： Duresti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

发明人： Duresti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

IPC分类号： H01L21/8238

CPC分类号： H01L29/1608 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/66651 ,  H01L29/7378 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/8086

摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.

摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。 在第一岛和第二岛上形成不同材料的层。 科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。 可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。

公开(公告)号：US07964865B2

公开(公告)日：2011-06-21

申请号：US11048739

申请日：2005-02-03

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci

IPC分类号： H01L29/06

CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L29/1054

摘要： A method for forming a semiconductor substrate structure is provided. A compressively strained SiGe layer is formed on a silicon substrate. Atoms are ion-implanted onto the SiGe layer to cause end-of-range damage. Annealing is performed to relax the strained SiGe layer. During the annealing, interstitial dislocation loops are formed as uniformly distributed in the SiGe layer. The interstitial dislocation loops provide a basis for nucleation of misfit dislocations between the SiGe layer and the silicon substrate. Since the interstitial dislocation loops are distributed uniformly, the misfit locations are also distributed uniformly, thereby relaxing the SiGe layer. A tensilely strained silicon layer is formed on the relaxed SiGe layer.

摘要翻译： 提供一种形成半导体衬底结构的方法。 在硅衬底上形成压缩应变SiGe层。 原子被离子注入SiGe层以造成范围内的损伤。 进行退火以松弛应变的SiGe层。 在退火过程中，间隙位错环形成均匀分布在SiGe层中。 间隙位错环为SiGe层和硅衬底之间的失配位错的成核提供了基础。 由于间隙位错环分布均匀，因此错位位置也均匀分布，从而松弛SiGe层。 在松弛的SiGe层上形成拉伸应变硅层。

公开(公告)号：US07816237B2

公开(公告)日：2010-10-19

申请号：US12132698

申请日：2008-06-04

申请人： Huajie Chen ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Werner A. Rausch

发明人： Huajie Chen ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Werner A. Rausch

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/26533 ,  H01L21/02238 ,  H01L21/26513 ,  H01L21/31654 ,  H01L21/31675 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/66636

摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

摘要翻译： 形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。 更具体地，本发明增加了硅衬底的顶表面的氧含量。 优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。 硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。 这允许本发明在硅​​衬底的顶表面上外延生长硅层。 此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。

公开(公告)号：US20090294854A1

公开(公告)日：2009-12-03

申请号：US12538111

申请日：2009-08-08

申请人： Omer H. Dokumaci ,  John M. Hergenrother ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Omer H. Dokumaci ,  John M. Hergenrother ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L29/786

CPC分类号： H01L29/66628 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78696

摘要： Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes.

摘要翻译： 通过在栅极再氧化步骤后立即进行晕圈注入，可获得对超薄绝缘体上的场效应晶体管（UTSOI-FET）的短沟道效应的优异控制。 然后形成偏移，然后执行延伸注入工艺。 这个处理步骤的顺序确保了晕轮植入物与延伸植入物横向分离偏移间隔物的宽度。 与传统的UTSOI-FET相比，这种结构产生等效或远优于短沟道性能。 另外，与常规方法相比，上述处理步骤允许使用较低的光晕剂量。

公开(公告)号：US20090261425A1

公开(公告)日：2009-10-22

申请号：US12106476

申请日：2008-04-21

申请人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Omer H. Dokumaci ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Omer H. Dokumaci ,  Edward J. Nowak

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/84

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L29/66803 ,  H01L29/785

摘要： A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins.

摘要翻译： 一种方法在绝缘体层上形成一对半导体翅片，然后在鳍片上并垂直于翅片形成线性栅极导体结构。 接下来，该方法在与鳍片相邻的绝缘体层上形成掩模，使得掩模的侧壁平行于翅片并与翅片间隔预定距离。 该方法对未被栅极导体结构和掩模保护的鳍片的区域进行倾斜的杂质注入。 该方法在翅片内形成不对称的杂质浓度，并且在相邻的翅片对中彼此相互镜像。

公开(公告)号：US07476946B2

公开(公告)日：2009-01-13

申请号：US11427222

申请日：2006-06-28

申请人： Andres Bryant ,  Omer H. Dokumaci ,  Hussein I Hanafi ,  Edward J. Nowak

发明人： Andres Bryant ,  Omer H. Dokumaci ,  Hussein I Hanafi ,  Edward J. Nowak

IPC分类号： H01L27/088

CPC分类号： H01L29/785 ,  H01L29/42368 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/7856

摘要： A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.

摘要翻译： 在前栅侧和后栅极侧制造具有不同介电层厚度的背景FinFET的方法包括将杂质引入FinFET的鳍的至少一侧的步骤，以形成不同厚度的电介质层。 可以通过注入引入的杂质增强或延迟电介质形成。

公开(公告)号：US07297601B2

公开(公告)日：2007-11-20

申请号：US11283882

申请日：2005-11-22

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/1054 ,  H01L29/6656

摘要： Method for manufacturing a semiconductor device. The method includes forming source and drain extension regions in an upper surface of a SiGe-based substrate. The source and drain extension regions contain an N type impurity. Reducing vacancy concentration in the source and drain extension regions to decrease diffusion of the N type impurity contained in the first source and drain extension regions.

摘要翻译： 半导体器件的制造方法 该方法包括在基于SiGe的衬底的上表面中形成源极和漏极延伸区域。 源极和漏极延伸区域包含N型杂质。 降低源极和漏极延伸区域中的空位浓度，以减少第一源极和漏极延伸区域中包含的N型杂质的扩散。

公开(公告)号：US07247534B2

公开(公告)日：2007-07-24

申请号：US10715400

申请日：2003-11-19

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

IPC分类号： H01L21/237 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/331 ,  H01L21/20 ,  H01L21/76

CPC分类号： H01L29/1608 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/66651 ,  H01L29/7378 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/8086

摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.

摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。 在第一岛和第二岛上形成不同材料的层。 科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。 可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。

公开(公告)号：US07223994B2

公开(公告)日：2007-05-29

申请号：US10859736

申请日：2004-06-03

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Huilong Zhu

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L21/0336

CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054

摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrate, a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.

摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括衬底，在衬底顶部的第一层叠堆叠，第一层叠堆叠包括衬底的第一含Si部分，衬底的含Si部分顶部的压缩层和半导体硅 层在压缩层顶上; 以及在所述衬底顶部的第二层叠叠层，所述第二层叠堆叠包括所述衬底的第二硅含有层部分，在所述衬底的所述第二含Si部分顶部的拉伸层，以及在所述拉伸层顶部的第二半导体硅层 。

公开(公告)号：US06329704B1

公开(公告)日：2001-12-11

申请号：US09458530

申请日：1999-12-09

申请人： Hiroyuki Akatsu ,  Omer H. Dokumaci ,  Suryanarayan G. Hegde ,  Yujun Li ,  Rajesh Rengarajan ,  Paul A. Ronsheim

发明人： Hiroyuki Akatsu ,  Omer H. Dokumaci ,  Suryanarayan G. Hegde ,  Yujun Li ,  Rajesh Rengarajan ,  Paul A. Ronsheim

IPC分类号： H01L29167

CPC分类号： H01L21/2652 ,  H01L21/2254 ,  H01L21/2255 ,  H01L29/6659

摘要： A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate. A low thermal budget is maintained because of the proximity of the as-implanted peak concentration to the interface and the presence of species implanted through the dielectric film and into the substrate.

摘要翻译： 一种用于在硅衬底内形成超浅结深度掺杂区的工艺。 该方法包括在衬底上形成电介质膜，然后将离子掺杂剂物质注入结构中。 植入物种的轮廓包括通过电介质膜注入硅衬底中的群体，以及刻意限制在电介质膜中的接近于介电膜和硅衬底之间界面的峰值浓度。 使用高能量，低剂量的植入工艺，并且产生基本上不含位错环和其它缺陷簇的结构。 使用退火工艺来驱动更接近界面的峰值浓度，以及从电介质膜到硅衬底的最初注入物质的一些群体。 由于植入的峰浓度与界面的接近以及通过电介质膜注入并进入衬底的物质的存在，维持了低热量预算。