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    Non-Volatile Magnetic Memory with Low Switching Current and High Thermal Stability
    61.
    发明申请
    Non-Volatile Magnetic Memory with Low Switching Current and High Thermal Stability 有权
    具有低开关电流和高热稳定性的非易失性磁存储器

    公开(公告)号：US20080191251A1

    公开(公告)日：2008-08-14

    申请号：US11739648

    申请日：2007-04-24

    申请人： Rajiv Yadav Ranjan ,  Parviz Keshtbod

    发明人： Rajiv Yadav Ranjan ,  Parviz Keshtbod

    IPC分类号： G11C11/22 ,  H01L43/12

    CPC分类号： H01L43/10 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228

    摘要： One embodiment of the present invention includes a an embodiment of the present invention includes a non-volatile current-switching magnetic memory element including a bottom electrode; a pinning layer formed on top of the bottom electrode; a fixed layer formed on top of the pinning layer; a tunnel layer formed on top of the pinning layer; a first free layer formed on top of the tunnel layer; a granular film layer formed on top of the free layer; a second free layer formed on top of the granular film layer; a cap layer formed on top of the second layer; and a top electrode formed on top of the cap layer.

    摘要翻译： 本发明的一个实施例包括本发明的一个实施例，其包括一个包括底部电极的非易失性电流切换磁存储元件; 形成在底部电极顶部的钉扎层; 形成在钉扎层顶部的固定层; 形成在钉扎层之上的隧道层; 形成在隧道层顶部的第一自由层; 形成在自由层顶部的粒状膜层; 形成在所述粒状膜层顶部的第二自由层; 盖层，形成在第二层的顶部; 以及形成在盖层顶部上的顶部电极。

    Redeposition control in MRAM fabrication process
    63.
    发明授权
    Redeposition control in MRAM fabrication process 有权
    MRAM制造工艺中的再沉积控制

    公开(公告)号：US08883520B2

    公开(公告)日：2014-11-11

    申请号：US13530381

    申请日：2012-06-22

    申请人： Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

    发明人： Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

    IPC分类号： H01L21/00

    CPC分类号： H01L43/02 ,  H01L27/222 ,  H01L43/12

    摘要： Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

    摘要翻译： 描述了方法和结构以在柱蚀刻期间减少存储器单元（例如MTJ电池）中的金属沉积材料。 一个实施例在位于晶片上暴露的金属表面的电介质层中的着陆焊盘的顶部上形成金属螺柱。 另一个实施例分别对MTJ和底部电极进行图案化。 底部电极掩模然后覆盖底部电极下面的金属。 另一实施例将柱蚀刻工艺分为两个阶段。 第一阶段蚀刻到较低的磁性层，然后阻挡层的侧壁被电介质材料覆盖，然后将其垂直蚀刻。 蚀刻的第二阶段然后对剩余的层进行图案化。 另一个实施例使用顶部电极上方的硬掩模来蚀刻MTJ柱直到靠近底部电极的端点，沉积电介质，然后垂直蚀刻剩余的底部电极。

    Multi-port magnetic random access memory (MRAM)
    65.
    发明授权
    Multi-port magnetic random access memory (MRAM) 有权
    多端口磁随机存取存储器（MRAM）

    公开(公告)号：US08670264B1

    公开(公告)日：2014-03-11

    申请号：US13585774

    申请日：2012-08-14

    申请人： Ebrahim Abedifard ,  Parviz Keshtbod

    发明人： Ebrahim Abedifard ,  Parviz Keshtbod

    IPC分类号： G11C11/21

    CPC分类号： G11C11/1673 ,  G11C8/16 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675

    摘要： A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

    摘要翻译： 存储器阵列被组织成电阻元件的行和列，并且被公开为包括要读取或要写入的电阻元件。 此外，第一存取晶体管耦合到电阻元件和第一源极线，第二存取晶体管耦合到电阻元件和第二源极线，电阻元件在一端被耦合到第一和第二存取 晶体管和位线的相对端。 存储器阵列还具有各自耦合到位线的其它电阻元件。 在读取其中一个或多个其它电阻元件的同时写入电阻元件。

    Method of sensing data of a magnetic random access memories (MRAM)
    66.
    发明授权
    Method of sensing data of a magnetic random access memories (MRAM) 有权
    用于检测磁随机存取存储器（MRAM）的数据的方法

    公开(公告)号：US08644060B2

    公开(公告)日：2014-02-04

    申请号：US13491159

    申请日：2012-06-07

    申请人： Ebrahim Abedifard ,  Parviz Keshtbod

    发明人： Ebrahim Abedifard ,  Parviz Keshtbod

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1673 ,  G11C11/1657

    摘要： A MTJ is sensed by applying a first reference current, first programming the MTJ to a first value using the first reference current, detecting the resistance of the first programmed MTJ, and if the detected resistance is above a first reference resistance, declaring the MTJ to be at a first state. Otherwise, upon determining if the detected resistance is below a second reference resistance, declaring the MTJ to be at a second state. In some cases, applying a second reference current through the MTJ and second programming the MTJ to a second value using the second reference current. Detecting the resistance of the second programmed MTJ and in some cases, declaring the MTJ to be at the second state, and in other cases, declaring the MTJ to be at the first state and programming the MTJ to the second state.

    摘要翻译： 通过施加第一参考电流来感测MTJ，首先使用第一参考电流将MTJ编程为第一值，检测第一编程MTJ的电阻，并且如果检测到的电阻高于第一参考电阻，则将MTJ声明为 处于第一个状态。 否则，在确定检测到的电阻是否低于第二参考电阻时，声明MTJ处于第二状态。 在某些情况下，通过MTJ施加第二参考电流，并使用第二参考电流对MTJ进行第二次编程。 检测第二个编程的MTJ的电阻，并且在某些情况下，声明MTJ处于第二状态，在其他情况下，声明MTJ处于第一状态并将MTJ编程到第二状态。

    Redeposition Control in MRAM Fabrication Process
    67.
    发明申请
    Redeposition Control in MRAM Fabrication Process 有权

    公开(公告)号：US20130341801A1

    公开(公告)日：2013-12-26

    申请号：US13530381

    申请日：2012-06-22

    申请人： Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

    发明人： Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

    IPC分类号： H01L23/498 ,  H01L21/768

    CPC分类号： H01L43/02 ,  H01L27/222 ,  H01L43/12

    摘要： Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.