公开(公告)号：US20170337984A1

公开(公告)日：2017-11-23

申请号：US15626040

申请日：2017-06-16

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Frederick A Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/24 ,  G11C29/50 ,  G06F11/10 ,  G11C29/44 ,  G11C5/04

CPC classification number: G06F11/1008 ,  G11C5/04 ,  G11C29/24 ,  G11C29/50016 ,  G11C2029/4402 ,  G11C2211/4061

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

公开(公告)号：US20140104935A1

公开(公告)日：2014-04-17

申请号：US14023970

申请日：2013-09-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G11C7/10 ,  G11C11/419 ,  G11C8/18

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/02 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1021 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/419 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract translation: 半导体存储器系统包括第一半导体存储器管芯和第二半导体存储器管芯。 第一半导体存储器管芯包括主数据接口，用于在写操作期间接收输入数据流，并将输入数据流反序列化为第一多个数据流，并且还包括耦合到主数据接口的辅数据接口， 发送第一多个数据流。 第二半导体存储器管芯包括耦合到第一半导体存储器管芯的次级数据接口的次级数据接口，以接收第一多个数据流。

公开(公告)号：US20250087261A1

公开(公告)日：2025-03-13

申请号：US18904454

申请日：2024-10-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408 ,  G06F12/06 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US12200860B2

公开(公告)日：2025-01-14

申请号：US18604133

申请日：2024-03-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan

IPC: G11C5/06 ,  G06F1/18 ,  G06F13/16 ,  G06F13/40 ,  G06F15/78 ,  G11C5/04 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4093 ,  H05K1/11 ,  H05K1/18

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

公开(公告)号：US20240276639A1

公开(公告)日：2024-08-15

申请号：US18604133

申请日：2024-03-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan

IPC: H05K1/11 ,  G06F1/18 ,  G06F13/16 ,  G06F13/40 ,  G06F15/78 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4093 ,  H05K1/18

CPC classification number: H05K1/11 ,  G06F1/184 ,  G06F13/1694 ,  G06F13/4068 ,  G06F15/7803 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4082 ,  G11C11/4093 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

公开(公告)号：US20240020258A1

公开(公告)日：2024-01-18

申请号：US18355660

申请日：2023-07-20

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

CPC classification number: G06F13/4022 ,  G06F13/1673 ,  G06F12/00 ,  G06F13/00 ,  G06F13/1694

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US20220398206A1

公开(公告)日：2022-12-15

申请号：US17809688

申请日：2022-06-29

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US20220322526A1

公开(公告)日：2022-10-06

申请号：US17726354

申请日：2022-04-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan

IPC: H05K1/11 ,  G11C11/4093 ,  H05K1/18 ,  G06F15/78 ,  G11C11/408 ,  G06F1/18 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G06F13/16 ,  G06F13/40

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

公开(公告)号：US11409682B2

公开(公告)日：2022-08-09

申请号：US16950861

申请日：2020-11-17

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US20210141748A1

公开(公告)日：2021-05-13

申请号：US17081909

申请日：2020-10-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G06F13/16 ,  G11C7/10 ,  G11C8/18 ,  G11C11/419 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G06F13/40

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.