公开(公告)号：US5691555A

公开(公告)日：1997-11-25

申请号：US598394

申请日：1996-02-08

Applicant: Raffaele Zambrano ,  Richard A. Blanchard

Inventor： Raffaele Zambrano ,  Richard A. Blanchard

IPC: H01L29/78

CPC classification number: H01L29/66712 ,  H01L29/7815

Abstract: In integrated structure sensing resistor for a power MOS device consists of a doped region extending from a deep body region of at least one cell of a first plurality of cells, constituting a main power device, to a deep body region of a corresponding cell of a second smaller plurality of cells constituting a current sensing device. The first plurality of cells and the second plurality of cells are formed using trench technology.

Abstract translation: 在用于功率MOS器件的集成结构感测电阻器中，包括从构成主电源器件的第一多个电池的至少一个电池的深体区域延伸到相应电池单元的深体区域的掺杂区域 构成电流感测装置的第二较小的多个单元。 使用沟槽技术形成第一多个单元和第二多个单元。

公开(公告)号：US5679587A

公开(公告)日：1997-10-21

申请号：US455492

申请日：1995-05-31

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L27/06 ,  H01L21/331 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L21/265

CPC classification number: H01L27/0821 ,  Y10S148/096

Abstract: An integrated circuit containing both power and small-signal NPN bipolar devices. The small-signal devices use lateral current flow, and are completely surrounded (laterally and vertically) by an N-type well region. The N-type well region itself is completely surrounded (laterally and vertically) by a P-type isolation region. This double isolation provides improved protection against turn-on of parasitic devices, which can cause leakage problems in the conventional device structures. Optionally a self-aligned process step is used to provide a graded base doping profile in the small-signal devices.

Abstract translation: 包含电源和小信号NPN双极器件的集成电路。 小信号装置使用横向电流，并被N型阱区完全包围（横向和垂直）。 N型井区本身被P型隔离区完全包围（横向和垂直）。 这种双重隔离提供了改进的防止寄生器件接通的保护，这可能导致传统器件结构中的泄漏问题。 可选地，使用自对准工艺步骤在小信号器件中提供渐变基极掺杂分布。

公开(公告)号：US5661430A

公开(公告)日：1997-08-26

申请号：US529805

申请日：1995-09-19

Applicant: Sergio Palara ,  Raffaele Zambrano

Inventor： Sergio Palara ,  Raffaele Zambrano

IPC: H01L27/04 ,  H01L27/02 ,  H01L29/78 ,  H03K17/08 ,  H03K17/687 ,  H03K17/16

CPC classification number: H01L27/0248

Abstract: An integrated circuit including a power stage, a low-voltage component separated from the power stage by an isolating region and a reference potential region at a reference potential. The power stage includes an N-type substrate region which may be biased to a terminal voltage with respect to the reference potential and the isolating region has P-type conductivity. The low-voltage component includes an N-type input region receiving an input voltage. The input voltage and the terminal voltage may oscillate a few tens of volts above or below the reference potential and turn on parasitic transistors. To prevent turning on of the parasitic transistors, switchable conductive paths are interposed between the isolating region on the one hand, and the substrate region, the input region and the reference potential region on the other, for electrically connecting the isolating region to one of the substrate region, input region and reference potential region which presents instant by instant the lowest potential.

Abstract translation: 一种集成电路，包括功率级，通过隔离区与功率级分离的低电压分量和参考电位的参考电位区。 功率级包括可以相对于参考电位偏置到端电压的N型衬底区域，并且隔离区域具有P型导电性。 低电压分量包括接收输入电压的N型输入区域。 输入电压和端子电压可能会振荡高于或低于参考电位几十伏，并接通寄生晶体管。 为了防止寄生晶体管的导通，可切换的导电路径一方面插入在隔离区域与另一方面的衬底区域，输入区域和参考电势区域之间，用于将隔离区域电连接到 衬底区域，输入区域和参考电位区域，其立即呈现最低电位。

公开(公告)号：US5597742A

公开(公告)日：1997-01-28

申请号：US442015

申请日：1995-05-16

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/761 ,  H01L27/082 ,  H01L21/265

CPC classification number: H01L27/0823 ,  H01L21/761

Abstract: The base region of the power stage and the horizontal isolation region of the integrated control circuit or collector region of a transistor of an integrated circuit consist of portions of an epitaxial layer with a first conductivity type grown in sequence on an underlying epitaxial layer with a second conductivity type opposite the first.

Abstract translation: 功率级的基极区域和集成电路的晶体管的集成控制电路或集电极区域的水平隔离区域由具有第一导电类型的外延层的部分依次生长在下面的外延层上，具有第二 导电类型与第一种相反。

公开(公告)号：US5585287A

公开(公告)日：1996-12-17

申请号：US458055

申请日：1995-06-01

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/331 ,  H01L27/06 ,  H01L29/735 ,  H01L21/265

CPC classification number: H01L29/6625 ,  H01L27/0623 ,  H01L29/735 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/126

Abstract: A bipolar control transistor, forming part of an integrated current-limiter device comprises inside an epitaxial layer superimposed over a semiconductor substrate of a first type of conductivity, a base region of a second type of conductivity accessible from a base contact and regions of collector and emitter of the first type of conductivity contained in the base region and accessible from respective collector and emitter contacts. The base region comprises at least one highly-doped deep-body region which contains almost completely said emitter region, a lightly-doped body region which contains the collector region and an intermediate-doped region which co-operates with the first deep-body region to completely contain the emitter region and a surface area of the base region that is included between the regions of collector and emitter. There is also at least one first portion of a layer of polysilicon superimposed and self-aligned with the surface area between the regions of collector and emitter and electrically connected to the collector contact of the bipolar transistor.

Abstract translation: 形成集成电流限制器件的一部分的双极性控制晶体管包括叠加在第一导电类型的半导体衬底上的外延层的内部，可从基极接触的第二类导电性的基极区域和集电极和 第一类电导率的发射极包含在基极区域中并且可从相应的集电极和发射极触点接近。 基极区域包括至少一个高度掺杂的深体区域，其包含几乎完全是所述发射极区域，包含集电极区域的轻掺杂体区域和与第一深体区域配合的中间掺杂区域 以完全包含发射极区域和包括在集电极和发射极的区域之间的基极区域的表面积。 还存在与集电极和发射极的区域之间的表面积叠置并自对准并与双极晶体管的集电极触点电连接的多晶硅层的至少一个第一部分。

公开(公告)号：US5556792A

公开(公告)日：1996-09-17

申请号：US472196

申请日：1995-06-07

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/76 ,  H01L27/088 ,  H01L29/78 ,  H01L21/70 ,  H01L49/00

CPC classification number: H01L27/088 ,  H01L2924/0002 ,  Y10S148/126

Abstract: A PIC structure includes a lightly doped semiconductor layer of the first conductivity type superimposed over a heavily doped semiconductor substrate of a second conductivity type, wherein a Vertical IGBT and a driving and control circuit including at least first conductivity type-channel MOSFETs are integrated. The MOSFETs are provided inside well regions of the second conductivity type which are included in at least one lightly doped region of the first conductivity type completely surrounded and isolated from the lightly doped layer of the first conductivity type by means of a respective isolated region of a second conductivity type.

Abstract translation: PIC结构包括叠加在第二导电类型的重掺杂半导体衬底上的第一导电类型的轻掺杂半导体层，其中垂直IGBT和包括至少第一导电类型沟道MOSFET的驱动和控制电路被集成。 所述MOSFET设置在所述第二导电类型的阱区域内，所述阱区域包括在所述第一导电类型的至少一个轻掺杂区域中，所述至少一个轻掺杂区域通过相应的隔离区域从所述第一导电类型的轻掺杂层完全包围和隔离 第二导电类型。

公开(公告)号：US5474944A

公开(公告)日：1995-12-12

申请号：US987759

申请日：1992-12-07

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L21/334

CPC classification number: H01L29/66712 ,  H01L29/7802 ,  H01L29/42368 ,  Y10S148/126

Abstract: A manufacturing process for an integrated circuit which includes at least one vertical-current-flow MOS transistor. The patterned photoresist which screens the body implant is also used to mask the etching of a nitride layer over a pad oxide. After the photoresist is cleared, the nitride pattern is transferred into the oxide, and the resulting oxide/nitride stack is used to mask the source implant. The nitride/oxide stack is then removed, the gate oxide is grown, and the gate layer is then deposited.

Abstract translation: 一种用于集成电路的制造方法，该集成电路包括至少一个垂直电流流量MOS晶体管。 屏蔽体植入物的图案化光致抗蚀剂还用于掩蔽衬垫氧化物上的氮化物层的蚀刻。 在光致抗蚀剂被清除之后，氮化物图案被转移到氧化物中，并且所得到的氧化物/氮化物堆叠用于掩蔽源植入物。 然后去除氮化物/氧化物堆叠，生长栅极氧化物，然后沉积栅极层。

公开(公告)号：US5382538A

公开(公告)日：1995-01-17

申请号：US66336

申请日：1993-05-21

Applicant: Raffaele Zambrano ,  Carmelo Magro

Inventor： Raffaele Zambrano ,  Carmelo Magro

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/66712 ,  H01L29/1095 ,  H01L29/7802 ,  Y10S148/126

Abstract: The process provides first for the accomplishment of low-doping body regions at the sides and under a gate region and then the accomplishment of high-doping body regions inside said low-doping body regions and self-aligned with said gate region. There is thus obtained an MOS power transistor with vertical current flow which has high-doping body regions self-aligned with said gate region and with a reduced junction depth.

Abstract translation: 该方法首先在侧面和栅极区域处实现低掺杂体区域，然后在所述低掺杂体区域内部实现高掺杂体区域并与所述栅极区域自对准。 因此获得了具有垂直电流的MOS功率晶体管，其具有与所述栅极区域自对准且具有减小的结深度的高掺杂体区域。

公开(公告)号：US5317182A

公开(公告)日：1994-05-31

申请号：US706751

申请日：1991-05-29

Applicant: Raffaele Zambrano ,  Antonio Grimaldi

Inventor： Raffaele Zambrano ,  Antonio Grimaldi

IPC: H01L21/8249 ,  H01L21/76 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/70

CPC classification number: H01L27/0623

Abstract: A smart power integrated circuit, in which the power stage includes a vertical-current-flow NMOS power transistor having many paralleled cells. A deeper P-type diffusion surrounds the P-type body region of the cells at the edge of the power stage. The junction between this deep P-type diffusion and the laterally adjacent N-type material has a lower curvature than the junction which would be formed by the P-type body region alone. This increases the transistor's breakdown voltage without degrading the transistor's on-state resistance R.sub.on.

Abstract translation: 一种智能功率集成电路，其中功率级包括具有许多并联单元的垂直电流流量NMOS功率晶体管。 更深的P型扩散围绕功率级边缘处的细胞的P型体区域。 该深P型扩散与横向相邻的N型材料之间的接合部的曲率比仅由P型体区域形成的接合点低。 这可以提高晶体管的击穿电压，而不会降低晶体管的导通电阻Ron。

公开(公告)号：US5300451A

公开(公告)日：1994-04-05

申请号：US967553

申请日：1992-10-27

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/336 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L29/66712 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/7802 ,  H01L29/0847 ,  Y10S148/126 ,  Y10S438/98

Abstract: The invention relates to a process for forming a buried drain or collector region in monolithic semiconductor devices comprising an integrated control circuit and one or more power transistors with vertical current flow integrated in the same chip. The process allows optimization of the current-carrying capacity and the series drain resistance of the power stage and operating voltage by the implantation of a buried gate region in a first epitaxial layer after the formation of said epitaxial layer. These buried gate regions high dopant concentrations where the dopants have low diffusion coefficients. These low diffusive dopants permit more accurate and form defined buried gate regions than current formation techniques utilizing formation of buried gate regions implemented in the substrate where these gate regions contain highly diffusive dopants.

Abstract translation: 本发明涉及一种用于在单片半导体器件中形成埋地漏极或集电极区域的方法，其包括集成控制电路和集成在同一芯片中的垂直电流的一个或多个功率晶体管。 该过程允许通过在形成所述外延层之后在第一外延层中注入掩埋栅极区域来优化功率级的载流能力和串联漏极电阻和工作电压。 这些掩埋栅区具有高掺杂浓度，其中掺杂剂具有低扩散系数。 这些低扩散掺杂剂允许比当前形成技术更精确和形成定义的掩埋栅极区域，其利用在衬底中实现的掩埋栅极区域的形成，其中这些栅极区域包含高度漫射掺杂剂。