公开(公告)号：US6138227A

公开(公告)日：2000-10-24

申请号：US43046

申请日：1998-03-13

申请人： Roland Thewes ,  Doris Schmitt-Landsiedel ,  Paul-Werner von Basse ,  Michael Bollu

发明人： Roland Thewes ,  Doris Schmitt-Landsiedel ,  Paul-Werner von Basse ,  Michael Bollu

IPC分类号： G11C8/04 ,  G06F12/02

CPC分类号： G11C8/04

摘要： A digital memory matrix having memory cells in rows and columns, addressing of the memory cells is accomplished by control devices which perform arbitrary jumps of address, thereby avoiding addressing on adjacent lines. The jump increment is selectable. The control devices are control chains, two of which are provided, and the outputs of the control chains are connected to linking elements that in turn are connected to the memory lines. The linking elements are provided in groups.

摘要翻译： PCT No.PCT / DE96 / 01511 Sec。 371日期1998年3月13日 102（e）1998年3月13日PCT PCT 1996年8月13日PCT公布。 公开号WO97 / 10600 日期1997年3月20日具有行和列的存储单元的数字存储器矩阵，存储器单元的寻址由执行地址的任意跳跃的控制设备实现，从而避免在相邻行上寻址。 跳跃增量可选。 控制装置是控制链，其中两个被提供，并且控制链的输出连接到链接元件，连接元件又连接到存储器线。 连接元件分组提供。

公开(公告)号：US6097661A

公开(公告)日：2000-08-01

申请号：US161004

申请日：1998-09-25

申请人： Roland Thewes ,  Doris Schmitt-Landsiedel ,  Paul-Werner von Basse ,  Michael Bollu ,  Ute Kollmer ,  Andreas Luck, deceased ,  by Manfred Luck, legal representative ,  by Inge Booken, legal representative

发明人： Roland Thewes ,  Doris Schmitt-Landsiedel ,  Paul-Werner von Basse ,  Michael Bollu ,  Ute Kollmer ,  Andreas Luck, deceased ,  by Manfred Luck, legal representative ,  by Inge Booken, legal representative

IPC分类号： G11C19/28 ,  G11C7/10 ,  G11C8/04 ,  G11C7/00

CPC分类号： G11C7/1018 ,  G11C8/04

摘要： In the pointer circuit, only one static memory (1) is respectively individually allocated to each output ( . . . , A.sub.n-1, A.sub.n, A.sub.n+1, . . . ), of which each respectively has a pair of mutually complementary memory terminals (Q, Q). The two terminals are in two stored logical states ("1," "0") differing from one another. A memory terminal (Q) of each memory is connected with the output allocated to this memory. The memories are controlled by clock signals. This results in advantageous surface requirement and power loss low, as well as high speed.

摘要翻译： 在指针电路中，只有一个静态存储器（1）分别分别分配给每个输出（...，An-1，An，An + 1，...），其中每个分别具有一对相互补充的存储器 端子（Q，+ E，ovs Q + EE）。 两个终端处于彼此不同的两个存储的逻辑状态（“1”，“0”）。 每个存储器的存储器端子（Q）与分配给该存储器的输出端连接。 存储器由时钟信号控制。 这导致有利的表面要求和功率损耗低以及高速度。

公开(公告)号：US5825686A

公开(公告)日：1998-10-20

申请号：US875955

申请日：1997-08-11

申请人： Doris Schmitt-Landsiedel ,  Roland Thewes ,  Michael Bollu ,  Paul-Werner von Basse

发明人： Doris Schmitt-Landsiedel ,  Roland Thewes ,  Michael Bollu ,  Paul-Werner von Basse

IPC分类号： G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L29/7923 ,  G11C11/56 ,  G11C11/5671 ,  G11C11/5692 ,  G11C16/0475

摘要： The invention concerns a multi-valued read-only storage location which is constructed symmetrically for storing a first or second state (M, M"') and asymmetrically for storing at least a third state (M', M"). The advantage thereof is above all that the storage capacity is doubled without notably increasing expenditure and without impairing the signal-to-noise ratio with respect to conventional storage locations. The invention is suitable for electrically programmable and mask-programmable read-only memories, in particular for those used in low voltage technology.

摘要翻译： PCT No.PCT / DE96 / 00168 Sec。 371日期1997年8月11日 102（e）日期1997年8月11日PCT 1996年2月5日PCT公布。 出版物WO96 / 25741 日期1996年8月22日本发明涉及一种多值只读存储位置，其被对称地构造用于存储第一或第二状态（M，M“'）并且不对称地用于存储至少第三状态（M'，M ''）。 其优点首先是在不显着增加支出的情况下将存储容量加倍，而不损害相对于常规存储位置的信噪比。 本发明适用于电可编程和掩模可编程只读存储器，特别是用于低电压技术的存储器。

公开(公告)号：US5732013A

公开(公告)日：1998-03-24

申请号：US780494

申请日：1997-01-08

申请人： Paul-Werner Von Basse ,  Roland Thewes ,  Doris Schmitt-Landsiedel ,  Michael Bollu

发明人： Paul-Werner Von Basse ,  Roland Thewes ,  Doris Schmitt-Landsiedel ,  Michael Bollu

IPC分类号： G11C8/10 ,  G11C17/12 ,  G11C17/00

CPC分类号： G11C8/10 ,  G11C17/126

摘要： A matrix memory with memory transistors arranged in rows and columns. The memory transistors can be addressed via word lines and bit lines. Control transistors are driven via control lines. The control transistors can short-circuit all of the columns of the cell array, i.e. the bit lines, except for the column in which a memory cell is located which is to be read out.

摘要翻译： 具有以行和列排列的存储晶体管的矩阵存储器。 可以通过字线和位线寻址存储晶体管。 控制晶体管通过控制线驱动。 控制晶体管可以短路单元阵列的所有列，即位线，除了要读出的存储单元所在的列之外。

公开(公告)号：US09135964B2

公开(公告)日：2015-09-15

申请号：US13456020

申请日：2012-04-25

申请人： Richard Ferrant ,  Roland Thewes

发明人： Richard Ferrant ,  Roland Thewes

IPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4094

CPC分类号： G11C7/065 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2211/4016

摘要： A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line complementary to the first bit line and a second CMOS inverter having an output connected to the second bit line (/BL) and an input connected to the first bit line. Each CMOS inverter includes pull-up and pull-down transistors, wherein the sources of either of the pull-up transistors or the pull-down transistors are electrically coupled and connected to a pull-up voltage source or a pull-down voltage source without an intermediate transistor between the sources of the transistors and the voltage source.

摘要翻译： 一种用于感测存储在存储单元阵列的多个存储单元中的数据的差分读出放大器，包括连接到第一位线（BL）的输出的第一CMOS反相器和连接到与第一位线互补的第二位线的输入端 位线和具有连接到第二位线（/ BL）的输出的第二CMOS反相器和连接到第一位线的输入。 每个CMOS反相器包括上拉和下拉晶体管，其中上拉晶体管或下拉晶体管中的任一个的源极电耦合并连接到上拉电压源或下拉电压源，而没有 在晶体管的源极和电压源之间的中间晶体管。

公开(公告)号：US08953399B2

公开(公告)日：2015-02-10

申请号：US13456047

申请日：2012-04-25

申请人： Richard Ferrant ,  Roland Thewes

发明人： Richard Ferrant ,  Roland Thewes

IPC分类号： G11C7/08 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4091

CPC分类号： G11C7/065 ,  G11C11/4091 ,  G11C2207/002

摘要： A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line. Each CMOS inverter includes a pull-up transistor and a pull-down transistor, and the sense amplifier has a pair of pass-gate transistors arranged to connect the first and second bit lines to a first and a second global bit lines. Advantageously, the pass-gate transistors are constituted by the pull-up transistors or the pull-down transistors.

摘要翻译： 一种用于感测存储在存储单元阵列的多个存储单元中的数据的差分读出放大器，包括连接到第一位线的输出的第一CMOS反相器和连接到与第一位线互补的第二位线的输入端， 以及具有连接到第二位线的输出和连接到第一位线的输入的第二CMOS反相器。 每个CMOS反相器包括上拉晶体管和下拉晶体管，并且读出放大器具有一对传输栅晶体管，被布置为将第一和第二位线连接到第一和第二全局位线。 有利的是，栅极晶体管由上拉晶体管或下拉晶体管构成。

公开(公告)号：US08702921B2

公开(公告)日：2014-04-22

申请号：US11019948

申请日：2004-12-21

申请人： Alexander Frey ,  Franz Hofmann ,  Birgit Holzapfl ,  Christian Paulus ,  Meinrad Schienle ,  Roland Thewes

发明人： Alexander Frey ,  Franz Hofmann ,  Birgit Holzapfl ,  Christian Paulus ,  Meinrad Schienle ,  Roland Thewes

IPC分类号： G01N27/26

CPC分类号： G01N27/3276

摘要： A biosensor array having a substrate, a plurality of biosensor zones arranged on the substrate, each of which has a first terminal and a second terminal, at least one drive line and at least one detection line, the at least one drive line being electrically insulated from the at least one detection line. In each case the first terminal of each biosensor zone is coupled to precisely one of the at least one drive line and the second terminal of each biosensor zone is coupled to precisely one of the at least one detection line, and at least one of the at least one drive line and at least one of the at least one detection line is coupled to at least two of the biosensor zones. The biosensor array also has a drive unit for providing an electrical drive signal, a detection unit for detecting an electrical detection signal resulting from the electrical drive signal, and a selection unit that couples the drive unit to the drive line of a biosensor zone to be selected and the detection unit to the detection line of the biosensor zone to be selected, whereby the biosensor zone is selected.

摘要翻译： 一种具有衬底的生物传感器阵列，布置在所述衬底上的多个生物传感器区域，每个生物传感器区域具有第一端子和第二端子，至少一条驱动线路和至少一条检测线路，所述至少一条驱动线路电绝缘 从所述至少一个检测线。 在每种情况下，每个生物传感器区域的第一端子被精确地耦合到至少一条驱动线路中的一条，并且每个生物传感器区域的第二端口精确地耦合到至少一条检测线路中的至少一条， 至少一个驱动线和所述至少一个检测线中的至少一个耦合到所述生物传感器区域中的至少两个。 生物传感器阵列还具有用于提供电驱动信号的驱动单元，用于检测由电驱动信号产生的电检测信号的检测单元，以及将驱动单元与生物传感器区域的驱动线连接的选择单元， 将选择的检测单元和生物传感器区域的检测线进行选择，从而选择生物传感器区域。

公开(公告)号：US20120275254A1

公开(公告)日：2012-11-01

申请号：US13456057

申请日：2012-04-25

申请人： Richard Ferrant ,  Roland Thewes

发明人： Richard Ferrant ,  Roland Thewes

IPC分类号： G11C7/06 ,  G11C7/08

CPC分类号： G11C7/065 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094

摘要： The invention relates to a differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line (BL). Each CMOS inverter includes a pull-up transistor and a pull-down transistor, with the sense amplifier having a pair of precharge transistors arranged to be respectively coupled to the first and second bit lines, to precharge the first and second bit lines to a precharge voltage. The precharge transistors are constituted by the pull-up transistors or by the pull-down transistors.

摘要翻译： 本发明涉及用于感测存储在存储单元阵列的多个存储器单元中的数据的差分读出放大器，包括具有连接到第一位线的输出的第一CMOS反相器和连接到与第一位线互补的第二位线的输入 第一位线和第二CMOS反相器，其具有连接到第二位线的输出和连接到第一位线（BL）的输入。 每个CMOS反相器包括一个上拉晶体管和一个下拉晶体管，其中读出放大器具有一对分别耦合到第一和第二位线的预充电晶体管，以将第一和第二位线预充电到预充电 电压。 预充电晶体管由上拉晶体管或下拉晶体管构成。

公开(公告)号：US07936628B2

公开(公告)日：2011-05-03

申请号：US12186085

申请日：2008-08-05

申请人： Helmut Schneider ,  Roland Thewes

发明人： Helmut Schneider ,  Roland Thewes

IPC分类号： G11C7/02

CPC分类号： G11C11/4097 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099 ,  G11C2207/005

摘要： A semiconductor memory having read amplifier strips having a plurality of read amplifiers and having memory cell fields which have a plurality of memory cells connected to bit lines is disclosed. The read amplifier strips include at least two outer read amplifier strips between which the remaining read amplifier strips and the memory cell fields are arranged, wherein adjacent to at least one of the outer read amplifier strips, a reference circuit field is arranged, which has reference lines and reference circuit elements connected thereto, and wherein the reference lines are shorter than the bit lines of the memory cell fields.

摘要翻译： 公开了一种具有多个读取放大器的读取放大器条带并且具有连接到位线的多个存储器单元的存储单元场的半导体存储器。 读取放大器条带包括至少两个外部读取放大器条带，其间布置剩余的读取放大器条带和存储器单元区域，其中与至少一个外部读取放大器条带相邻，配置参考电路字段，其具有参考 线路和参考电路元件，并且其中参考线比存储器单元场的位线短。

公开(公告)号：US07670557B2

公开(公告)日：2010-03-02

申请号：US11631380

申请日：2005-06-30

申请人： Alexander Frey ,  Christian Paulus ,  Meinrad Schienle ,  Roland Thewes

发明人： Alexander Frey ,  Christian Paulus ,  Meinrad Schienle ,  Roland Thewes

IPC分类号： G01N31/00

CPC分类号： G01N33/5438 ,  G01N27/02 ,  G01N27/3276

摘要： A planar-sensor arrangement is disclosed, which is used to detect particles possibly contained in an analyte. The sensor element includes a substrate, a first planar-sensor electrode and a second planar-sensor electrode which are formed on and/or in the substrate and whereon catcher molecules can be immobilized. The first sensor-electrode and the second sensor-electrode are divided, respectively, into a plurality of planar sensor-electrode partial areas. The sensor electrode partial areas of the first sensor electrode and the sensor electrode partial areas of the second sensor electrode are arranged in an alternating manner in two dimensions on the surface plane of the substrate. The sensor element also includes a wiring structure by which at least one part of the sensor electrode partial areas of the first sensor electrode are electrically coupled together, and by which at least one part of the sensor-electrode partial areas of the second sensor electrode are electrically coupled together.

摘要翻译： 公开了一种平面传感器装置，其用于检测可能包含在分析物中的颗粒。 传感器元件包括衬底，第一平面传感器电极和第二平面传感器电极，其形成在衬底上和/或衬底中，并且捕获剂分子可以被固定。 第一传感器电极和第二传感器电极分别分成多个平面传感器电极部分区域。 第一传感器电极的传感器电极部分区域和第二传感器电极的传感器电极部分区域在基板的表面上以二维交替排列。 传感器元件还包括布线结构，通过该布线结构，传感器电极的至少一部分第一传感器电极的部分区域电耦合在一起，并且第二传感器电极的传感器电极部分区域的至少一部分 电耦合在一起。