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公开(公告)号：US5751742A
公开(公告)日：1998-05-12
申请号：US626512
申请日：1996-04-02
CPC分类号： G11C29/86 , G06F11/1008 , G11C29/88
摘要： In a serially working memory unit with a memory matrix, a row selection unit and a column selection unit are configured such that, given faulty rows or columns, only correctable, single errors or errors of few successive bits occur. This memory unit offers advantages particularly for read-only memories since, due to the memory contents that are already determined during manufacture, substitute rows or columns can thereby not be provided.
摘要翻译： 在具有存储器矩阵的串行工作存储器单元中，行选择单元和列选择单元被配置为使得给定有故障的行或列仅发生少数连续位的可校正的单个错误或错误。 该存储单元特别对于只读存储器提供了优点，因为由于在制造期间已经确定的存储器内容，因此可以不提供代替行或列。
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2.发明授权
公开(公告)号：US5825701A
公开(公告)日：1998-10-20
申请号：US682022
申请日：1996-07-16
IPC分类号： G11C11/412 , G11C7/12 , G11C17/12 , G11C7/00
CPC分类号： G11C7/12 , G11C17/126
摘要： The memory cell arrangement has MOS transistors (10) connected between bitlines (4, 4.sub.1) and connected row-by-row by means of selection lines (5). For pre-charging of all the bitlines (4, 4.sub.1) without a blocking of an access to these lines, further MOS transistors (20), connected between the bitlines (4, 4.sub.1) and a supply line (7), are provided, whose gate terminals (20.sub.2) are connected to a common pre-charging line (6).
摘要翻译： 存储单元布置具有连接在位线（4,41）之间并通过选择线（5）逐行连接的MOS晶体管（10）。 为了对所有位线（4,41）进行预充电而不阻塞访问这些线路，连接在位线（4,41）和电源线（7）之间的另外的MOS晶体管（20）被提供， 其栅极端子（202）连接到公共预充电线（6）。
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3.发明授权Device for the jump-like addressing of specific lines of a serially operating digital memory 失效用于串行操作数字存储器的特定线路的跳转寻址的设备
公开(公告)号：US6138227A
公开(公告)日：2000-10-24
申请号：US43046
申请日：1998-03-13
CPC分类号： G11C8/04
摘要： A digital memory matrix having memory cells in rows and columns, addressing of the memory cells is accomplished by control devices which perform arbitrary jumps of address, thereby avoiding addressing on adjacent lines. The jump increment is selectable. The control devices are control chains, two of which are provided, and the outputs of the control chains are connected to linking elements that in turn are connected to the memory lines. The linking elements are provided in groups.
摘要翻译： PCT No.PCT / DE96 / 01511 Sec。 371日期1998年3月13日 102（e）1998年3月13日PCT PCT 1996年8月13日PCT公布。 公开号WO97 / 10600 日期1997年3月20日具有行和列的存储单元的数字存储器矩阵，存储器单元的寻址由执行地址的任意跳跃的控制设备实现，从而避免在相邻行上寻址。 跳跃增量可选。 控制装置是控制链，其中两个被提供，并且控制链的输出连接到链接元件，连接元件又连接到存储器线。 连接元件分组提供。
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4.发明授权
公开(公告)号：US6097661A
公开(公告)日：2000-08-01
申请号：US161004
申请日：1998-09-25
申请人： Roland Thewes , Doris Schmitt-Landsiedel , Paul-Werner von Basse , Michael Bollu , Ute Kollmer , Andreas Luck, deceased , by Manfred Luck, legal representative , by Inge Booken, legal representative
发明人： Roland Thewes , Doris Schmitt-Landsiedel , Paul-Werner von Basse , Michael Bollu , Ute Kollmer , Andreas Luck, deceased , by Manfred Luck, legal representative , by Inge Booken, legal representative
CPC分类号： G11C7/1018 , G11C8/04
摘要： In the pointer circuit, only one static memory (1) is respectively individually allocated to each output ( . . . , A.sub.n-1, A.sub.n, A.sub.n+1, . . . ), of which each respectively has a pair of mutually complementary memory terminals (Q, Q). The two terminals are in two stored logical states ("1," "0") differing from one another. A memory terminal (Q) of each memory is connected with the output allocated to this memory. The memories are controlled by clock signals. This results in advantageous surface requirement and power loss low, as well as high speed.
摘要翻译： 在指针电路中，只有一个静态存储器（1）分别分别分配给每个输出（...，An-1，An，An + 1，...），其中每个分别具有一对相互补充的存储器 端子（Q，+ E，ovs Q + EE）。 两个终端处于彼此不同的两个存储的逻辑状态（“1”，“0”）。 每个存储器的存储器端子（Q）与分配给该存储器的输出端连接。 存储器由时钟信号控制。 这导致有利的表面要求和功率损耗低以及高速度。
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5.发明授权
公开(公告)号：US5825686A
公开(公告)日：1998-10-20
申请号：US875955
申请日：1997-08-11
IPC分类号： G11C11/56 , G11C16/02 , G11C16/04 , H01L29/792 , G11C11/34
CPC分类号： H01L29/7923 , G11C11/56 , G11C11/5671 , G11C11/5692 , G11C16/0475
摘要： The invention concerns a multi-valued read-only storage location which is constructed symmetrically for storing a first or second state (M, M"') and asymmetrically for storing at least a third state (M', M"). The advantage thereof is above all that the storage capacity is doubled without notably increasing expenditure and without impairing the signal-to-noise ratio with respect to conventional storage locations. The invention is suitable for electrically programmable and mask-programmable read-only memories, in particular for those used in low voltage technology.
摘要翻译： PCT No.PCT / DE96 / 00168 Sec。 371日期1997年8月11日 102（e）日期1997年8月11日PCT 1996年2月5日PCT公布。 出版物WO96 / 25741 日期1996年8月22日本发明涉及一种多值只读存储位置，其被对称地构造用于存储第一或第二状态（M，M“'）并且不对称地用于存储至少第三状态（M'，M ''）。 其优点首先是在不显着增加支出的情况下将存储容量加倍，而不损害相对于常规存储位置的信噪比。 本发明适用于电可编程和掩模可编程只读存储器，特别是用于低电压技术的存储器。
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公开(公告)号：US5732013A
公开(公告)日：1998-03-24
申请号：US780494
申请日：1997-01-08
CPC分类号： G11C8/10 , G11C17/126
摘要： A matrix memory with memory transistors arranged in rows and columns. The memory transistors can be addressed via word lines and bit lines. Control transistors are driven via control lines. The control transistors can short-circuit all of the columns of the cell array, i.e. the bit lines, except for the column in which a memory cell is located which is to be read out.
摘要翻译： 具有以行和列排列的存储晶体管的矩阵存储器。 可以通过字线和位线寻址存储晶体管。 控制晶体管通过控制线驱动。 控制晶体管可以短路单元阵列的所有列，即位线，除了要读出的存储单元所在的列之外。
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公开(公告)号：US06181183B2
公开(公告)日：2001-01-30
申请号：US09269047
申请日：1999-03-18
IPC分类号： H03K513
CPC分类号： H03K5/133
摘要： A circuit with a delay stage formed by an invertor having high-impedance transistors and, connected in series therewith, an invertor having low-impedance transistors MOS capacitors are provided between the gates of the transistors of the low-impedance invertor and the output of the delay stage. By means of this circuit, delay stages with steep edges can be realized with comparatively less outlay on components.
摘要翻译： 具有由具有高阻抗晶体管的反相器形成的延迟级的电路设置在低阻抗反相器的晶体管的栅极和 延迟阶段 通过该电路，可以实现具有陡峭边缘的延迟级，而在组件上的相对较少的支出。
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公开(公告)号：US5831892A
公开(公告)日：1998-11-03
申请号：US904373
申请日：1997-08-01
CPC分类号： G11C17/126 , G11C11/56 , G11C11/5692 , G11C16/0491 , G11C2211/5631 , G11C2211/5634 , G11C7/1006
摘要： A matrix memory with improved virtual ground architecture and evaluation circuit from which the informational content of two neighboring memory cells can be simultaneously read at a bit line during a read event. The memory cells with information "0" are realized, for example, by a respective field effect transistor with low threshold voltage. Every bit line provided for the readout is connected to the drain terminals of two neighboring field effect transistors in the same row. The source terminals are applied to one of two potentials that differ from one another. Depending upon which of the field effect transistors is conductive upon selection of the pertinent word line, different resultant potentials are obtained on the bit line. Such potentials are then converted in the evaluation circuit into binary signals that represent the read information.
摘要翻译： 具有改进的虚拟地面架构和评估电路的矩阵存储器，可以在读取事件期间在位线上同时读取两个相邻存储器单元的信息内容。 具有信息“0”的存储单元例如由具有低阈值电压的各自的场效应晶体管实现。 为读出提供的每个位线连接到同一行中的两个相邻场效应晶体管的漏极端子。 源端子被施加到彼此不同的两个电位之一。 取决于在选择相关字线时场效应晶体管是导通的，在位线上获得不同的合成电位。 然后将这些电位在评估电路中转换为表示读取信息的二进制信号。
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公开(公告)号：US6044006A
公开(公告)日：2000-03-28
申请号：US273648
申请日：1999-03-23
CPC分类号： G11C16/10
摘要： Memory cells are organized in cell fields in word lines and bit lines in the manner of a matrix. The bit lines are actuated by a bit decoder for loading with a mass potential, and by a blocking decoder for loading the bit lines with a blocking potential. The word lines are actuated by a word decoder for loading the word lines with a programming voltage or a protective voltage. The information value to be programmed is prestored in the cell field.
摘要翻译： 存储单元以矩阵的方式组织在字线和位线的单元格区域中。 位线由用于加载质量电位的位解码器以及用于加载具有阻塞电位的位线的阻塞解码器来驱动。 字线由字解码器驱动，用于用编程电压或保护电压加载字线。 要编程的信息值预先存储在单元格区域中。
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公开(公告)号：US08125821B2
公开(公告)日：2012-02-28
申请号：US11756639
申请日：2007-06-01
申请人： Jan Otterstedt , Thomas Nirschl , Christian Peters , Michael Bollu , Wolf Allers , Michael Sommer
发明人： Jan Otterstedt , Thomas Nirschl , Christian Peters , Michael Bollu , Wolf Allers , Michael Sommer
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0078 , G11C2213/15 , G11C2213/79
摘要： One or more embodiments are related to a method of operating a phase-change memory array, including: providing the phase-change memory array, the phase-change memory array including a phase-change memory element in series with an access device between a first address line and a power line; causing a first current through the memory element from the first address line to the power line; and causing a second current through the memory element from the power line to the first address line.
摘要翻译： 一个或多个实施例涉及一种操作相变存储器阵列的方法，包括：提供相变存储器阵列，所述相变存储器阵列包括与存取装置串联的相变存储器元件，位于第一 地址线和电力线; 引起从第一地址线到电力线的存储元件的第一电流; 并且引起从电力线到第一地址线的存储元件的第二电流。
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