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159 条记录 (耗时 0.046 秒)

    Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process
    62.
    发明授权
    Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process 有权
    在普通蚀刻工艺中用于图案化垂直接触和金属线的半导体器件和方法

    公开(公告)号：US08741770B2

    公开(公告)日：2014-06-03

    申请号：US13468083

    申请日：2012-05-10

    申请人： Ralf Richter ,  Robert Seidel ,  Juergen Boemmels ,  Thomas Foltyn

    发明人： Ralf Richter ,  Robert Seidel ,  Juergen Boemmels ,  Thomas Foltyn

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/7681 ,  H01L21/76811 ,  H01L21/76816

    摘要： Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.

    摘要翻译： 中间层连接（即垂直连接）可以基于硬掩模材料形成，硬掩模材料可以位于层间电介质材料的内部或之上，其中一个横向尺寸由沟槽掩模限定，从而获得所需的中间层 连接在共同的图案化过程中。 此外，金属线的至少某些部分的厚度可以以高度的柔性来调节，从而提供了显着降低金属线中金属线的整体电阻率的可能性，其中器件性能可能显着地取决于电阻率 比寄生电容。

    METHODS FOR DEPOSITION OF TUNGSTEN IN THE FABRICATION OF AN INTEGRATED CIRCUIT
    64.
    发明申请
    METHODS FOR DEPOSITION OF TUNGSTEN IN THE FABRICATION OF AN INTEGRATED CIRCUIT 审中-公开
    在集成电路制造中沉积钨铁的方法

    公开(公告)号：US20130224948A1

    公开(公告)日：2013-08-29

    申请号：US13406566

    申请日：2012-02-28

    申请人： Ralf Richter ,  Jana Rössler

    发明人： Ralf Richter ,  Jana Rössler

    IPC分类号： H01L21/768

    CPC分类号： H01L21/7684 ,  H01L21/76877

    摘要： A method for fabricating an integrated circuit includes providing a semiconductor wafer comprising a hole etched therein, depositing a first layer comprising tungsten onto the semiconductor wafer and into the hole therein, thereby filling the hole with the first layer, and etching the first layer from the semiconductor wafer, wherein etching the first layer results in the formation of a divot above the first layer within the hole. The method may further include depositing a second layer comprising tungsten onto the semiconductor wafer and into the divot formed above the first layer within the hole and polishing the second layer from the semiconductor wafer, wherein polishing the second layer does not remove the second layer deposited into the divot.

    摘要翻译： 一种用于制造集成电路的方法包括：提供包括蚀刻在其中的孔的半导体晶片，将包含钨的第一层沉积到半导体晶片上并进入其中的孔中，由此用第一层填充该孔，并从第 半导体晶片，其中蚀刻第一层导致在孔内的第一层上方形成凹陷。 该方法还可以包括将包含钨的第二层沉积到半导体晶片上并进入在孔内的第一层上方形成的凹槽中，并从半导体晶片抛光第二层，其中抛光第二层不会去除沉积在第二层中的第二层 神话

    Non-insulating stressed material layers in a contact level of semiconductor devices
    65.
    发明授权
    Non-insulating stressed material layers in a contact level of semiconductor devices 有权
    非绝缘应力材料层在半导体器件的接触电平

    公开(公告)号：US08450172B2

    公开(公告)日：2013-05-28

    申请号：US12823660

    申请日：2010-06-25

    申请人： Ralf Richter ,  Hartmut Ruelke ,  Joerg Hohage

    发明人： Ralf Richter ,  Hartmut Ruelke ,  Joerg Hohage

    IPC分类号： H01L21/8238 ,  H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823425 ,  H01L29/7843

    摘要： In sophisticated semiconductor devices, non-insulating materials with extremely high internal stress level may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors, wherein the non-insulating material may be appropriately “encapsulated” by dielectric material. Consequently, a desired high strain level may be obtained on the basis of a reduced layer thickness, while still providing the insulating characteristics required in the contact level.

    摘要翻译： 在复杂的半导体器件中，可以在接触电平中使用具有非常高的内部应力水平的非绝缘材料，以便增强诸如场效应晶体管的电路元件的性能，其中非绝缘材料可以被适当地“封装” 介电材料。 因此，可以基于减小的层厚度获得期望的高应变水平，同时仍然提供接触水平所需的绝缘特性。

    Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors
    66.
    发明授权
    Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors 失效
    在紧密间隔的晶体管的接触电平中的介电材料的图案化期间减小与形貌相关的不规则性的技术

    公开(公告)号：US08338314B2

    公开(公告)日：2012-12-25

    申请号：US12372006

    申请日：2009-02-17

    申请人： Ralf Richter ,  Heike Salz ,  Robert Seidel

    发明人： Ralf Richter ,  Heike Salz ,  Robert Seidel

    IPC分类号： H01L21/31

    CPC分类号： H01L21/02107 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/51 ,  H01L29/7843 ,  H01L29/7848 ,  Y02P80/30

    摘要： In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.

    摘要翻译： 在双重应力衬垫方法中，可以通过适当地设计用于基本上完全去除蚀刻停止材料的蚀刻顺序来增强第一应力诱导层的图案化之后的表面状态，所述蚀刻顺序可用于图案化第二应力 - 诱导介电材料，而在其它情况下，可以在第一应力诱导电介质材料的图案化之后选择性地形成蚀刻停止材料。 因此，双重应力衬垫方法可以有效地应用于45nm技术及其以外的半导体器件。

    Using high-k dielectrics as highly selective etch stop materials in semiconductor devices
    67.
    发明授权
    Using high-k dielectrics as highly selective etch stop materials in semiconductor devices 有权
    使用高k电介质作为半导体器件中的高选择性蚀刻停止材料

    公开(公告)号：US08198166B2

    公开(公告)日：2012-06-12

    申请号：US12844135

    申请日：2010-07-27

    申请人： Thorsten Kammler ,  Ralf Richter ,  Markus Lenski ,  Gunter Grasshoff

    发明人： Thorsten Kammler ,  Ralf Richter ,  Markus Lenski ,  Gunter Grasshoff

    IPC分类号： H01L21/00

    CPC分类号： H01L29/4983 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843

    摘要： A spacer structure in sophisticated semiconductor devices is formed on the basis of a high-k dielectric material, which provides superior etch resistivity compared to conventionally used silicon dioxide liners. Consequently, a reduced thickness of the etch stop material may nevertheless provide superior etch resistivity, thereby reducing negative effects, such as dopant loss in the drain and source extension regions, creating a pronounced surface topography and the like, as are typically associated with conventional spacer material systems.

    摘要翻译： 在高k电介质材料的基础上形成复杂半导体器件中的间隔结构，其与传统使用的二氧化硅衬垫相比提供了优异的蚀刻电阻率。 因此，蚀刻停止材料的厚度减小可以提供优异的蚀刻电阻率，从而减少负面影响，例如漏极和源极延伸区域中的掺杂剂损失，产生显着的表面形貌等，如通常与常规间隔物相关联 材料系统