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    MULTI-GATE DEVICE HAVING A T-SHAPED GATE STRUCTURE
    63.
    发明申请
    MULTI-GATE DEVICE HAVING A T-SHAPED GATE STRUCTURE 有权
    具有T形门结构的多门装置

    公开(公告)号：US20090206406A1

    公开(公告)日：2009-08-20

    申请号：US12032603

    申请日：2008-02-15

    申请人： Willy Rachmady ,  Uday Shah ,  Jack T. Kavalieros

    发明人： Willy Rachmady ,  Uday Shah ,  Jack T. Kavalieros

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/42376 ,  H01L21/28114 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    摘要： A multi-gate device having a T-shaped gate structure is generally described. In one example, an apparatus includes a semiconductor substrate, at least one multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a gate region, a source region, and a drain region, the gate region being positioned between the source and drain regions, a gate dielectric coupled to the gate region of the multi-gate fin, a gate electrode coupled to the gate dielectric, the gate electrode having a first thickness and a second thickness, the second thickness being greater than the first thickness, a first spacer dielectric coupled to a portion of the gate electrode having the first thickness, and a second spacer dielectric coupled to the first spacer dielectric and coupled to the gate electrode where the second spacer dielectric is coupled to a portion of the gate electrode having the second thickness.

    摘要翻译： 通常描述具有T形门结构的多栅极器件。 在一个示例中，设备包括半导体衬底，与半导体衬底耦合的至少一个多栅极鳍，多栅极鳍具有栅极区，源极区和漏极区，栅极区位于 源极和漏极区域，耦合到多栅极鳍的栅极区域的栅极电介质，耦合到栅极电介质的栅电极，栅电极具有第一厚度和第二厚度，第二厚度大于第一厚度 耦合到具有第一厚度的栅电极的一部分的第一间隔电介质和耦合到第一间隔电介质并耦合到栅电极的第二间隔电介质，其中第二间隔电介质耦合到栅电极的一部分， 第二厚度。

    FABRICATING DUAL LAYER GATE ELECTRODES HAVING POLYSILICON AND A WORKFUNCTION METAL
    64.
    发明申请
    FABRICATING DUAL LAYER GATE ELECTRODES HAVING POLYSILICON AND A WORKFUNCTION METAL 审中-公开
    制造具有多晶硅和工作金属的双层门电极

    公开(公告)号：US20090061611A1

    公开(公告)日：2009-03-05

    申请号：US11848239

    申请日：2007-08-30

    申请人： Willy Rachmady ,  Uday Shah ,  Jack T. Kavalieros ,  Brian S. Doyle

    发明人： Willy Rachmady ,  Uday Shah ,  Jack T. Kavalieros ,  Brian S. Doyle

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/4958 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/66795 ,  H01L29/785

    摘要： A method for fabricating a dual layer gate electrode having a polysilicon layer and a workfunction metal layer comprises depositing a layer of a workfunction metal on a semiconductor substrate, depositing a layer of polysilicon on the workfunction metal layer, depositing a hard mask layer on the polysilicon layer, etching the hard mask layer to form a hard mask structure defining a gate electrode, etching the polysilicon layer to remove a portion of the polysilicon layer not protected by the hard mask structure, thereby forming a polysilicon structure beneath the hard mask structure, applying a mixture of ozone and water to exposed sidewalls of the polysilicon structure, thereby forming a silicon dioxide layer on the sidewalls, and etching the workfunction metal layer to remove a portion of the workfunction metal layer not protected by the hard mask structure, thereby forming a workfunction metal structure beneath the polysilicon structure.

    摘要翻译： 一种用于制造具有多晶硅层和功函数金属层的双层栅电极的方法，包括在半导体衬底上沉积功函数金属层，在功函数金属层上沉积多晶硅层，在多晶硅上沉积硬掩模层 蚀刻硬掩模层以形成限定栅电极的硬掩模结构，蚀刻多晶硅层以去除未被硬掩模结构保护的多晶硅层的一部分，从而在硬掩模结构下方形成多晶硅结构，施加 将臭氧和水的混合物混合到多晶硅结构的暴露的侧壁，从而在侧壁上形成二氧化硅层，并蚀刻功函数金属层以除去未被硬掩模结构保护的功能金属层的一部分，从而形成 多晶硅结构下面的功函数金属结构。

    Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin
    70.
    发明授权
    Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin 有权
    通过结合部分金属翅片来减少多栅极器件的外部电阻

    公开(公告)号：US07763943B2

    公开(公告)日：2010-07-27

    申请号：US11964623

    申请日：2007-12-26

    申请人： Ravi Pillarisetty ,  Uday Shah ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

    发明人： Ravi Pillarisetty ,  Uday Shah ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.

    摘要翻译： 通常描述通过结合部分金属翅片来降低多栅极器件的外部电阻。 在一个示例中，设备包括半导体衬底和与半导体衬底耦合的多栅极晶体管器件的一个或多个鳍片，该一个或多个鳍片具有栅极区域，源极区域和漏极区域，栅极区域 设置在源极和漏极区域之间，其中一个或多个鳍片的栅极区域包括半导体材料，并且其中一个或多个鳍片的源极和漏极区域包括金属部分和半导体部分，金属部分和半导体 部分联接在一起。