公开(公告)号：US07612630B2

公开(公告)日：2009-11-03

申请号：US11058486

申请日：2005-02-15

申请人： Charles A. Miller

发明人： Charles A. Miller

IPC分类号： H01P5/02 ,  H01P5/18

CPC分类号： H04B5/0012 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/3011 ,  H04B5/0075 ,  H04B5/02 ,  H05K1/141 ,  H05K1/181 ,  H05K3/366 ,  H05K2201/10098 ,  Y02P70/611 ,  H01L2924/00

摘要： An electromagnetic interconnect method and apparatus effects contactless, proximity connections between elements in an electronics system. Data to be communicated between elements in an electronic system are modulated into a carrier signal and transmitted contactlessly by electromagnetic coupling. The electromagnetic coupling may be directly between elements in the system or through an intermediary transmission medium.

公开(公告)号：US07583101B2

公开(公告)日：2009-09-01

申请号：US11624661

申请日：2007-01-18

申请人： Charles A. Miller

发明人： Charles A. Miller

IPC分类号： G01R31/02

CPC分类号： G01R1/07342 ,  G01R1/06727 ,  Y10T29/49002

摘要： A microelectronic resilient structure can comprise a support member and a platform attached to the support member. The platform can comprise a non-conductive, resilient beam that extends away from the support member, and a plurality of conductive members can be disposed on the beams. The conductive members can extend along a length of the beam. A plurality of conductive contact elements can be disposed on the beam and electrically connected to one of the conductive members.

摘要翻译： 微电子弹性结构可以包括支撑构件和附接到支撑构件的平台。 平台可以包括远离支撑构件延伸的非导电弹性梁，并且可以在梁上设置多个导电构件。 导电构件可以沿着梁的长度延伸。 多个导电接触元件可以设置在梁上并电连接到导电构件之一。

公开(公告)号：US07557592B2

公开(公告)日：2009-07-07

申请号：US11422573

申请日：2006-06-06

申请人： Charles A. Miller

发明人： Charles A. Miller

IPC分类号： G01R31/02 ,  G01R31/26

CPC分类号： G01R31/2889 ,  G01R1/07342

摘要： A probe card assembly can comprise an interface, which can be configured to receive from a tester test signals for testing an electronic device. The probe card assembly can further comprise probes for contacting the electronic device and electronic driver circuits for driving the test signals to ones of the probes.

摘要翻译： 探针卡组件可以包括接口，其可以被配置为从测试仪接收测试用于测试电子设备的信号。 探针卡组件还可以包括用于接触电子设备的探针和用于将测试信号驱动到探针中的探针的电子驱动器电路。

公开(公告)号：US07548055B2

公开(公告)日：2009-06-16

申请号：US11696582

申请日：2007-04-04

申请人： Igor Y. Khandros ,  Benjamin N. Eldridge ,  Charles A. Miller ,  A. Nicholas Sporck

发明人： Igor Y. Khandros ,  Benjamin N. Eldridge ,  Charles A. Miller ,  A. Nicholas Sporck

IPC分类号： G01R31/28

CPC分类号： G01R1/0491 ,  G01R1/073 ,  G01R31/3025

摘要： A method and apparatus for testing a set of electronic devices can comprise placing electronic devices into a test station. A plurality of testers can provide test data to the test station. The test station can test the electronic devices using test data received from the plurality of testers. One of the testers can communication with another of the testers regarding the testing of the electronic devices. Probes can be used to contact the electronic devices, and one of the electronic devices can be contacted by more than one of the probes.

摘要翻译： 用于测试一组电子设备的方法和装置可以包括将电子设备放置在测试台中。 多个测试者可以向测试台提供测试数据。 测试台可以使用从多个测试器接收的测试数据来测试电子设备。 其中一个测试人员可以与其他测试人员进行电子设备测试的通信。 探针可用于接触电子设备，并且其中一个电子设备可以被多个探针接触。

公开(公告)号：US07508227B2

公开(公告)日：2009-03-24

申请号：US11866024

申请日：2007-10-02

申请人： Charles A. Miller ,  John Matthew Long

发明人： Charles A. Miller ,  John Matthew Long

IPC分类号： G01R1/073 ,  G01R31/28

CPC分类号： G01R31/31926 ,  G01R1/07378 ,  G01R31/318511 ,  G11C29/56 ,  G11C2029/2602 ,  H05K1/0216 ,  H05K1/023 ,  H05K1/0289 ,  H05K2201/09254 ,  Y10T29/49117

摘要： An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.

摘要翻译： 互连结构采用闭合栅格总线将集成电路测试器通道连接到半导体晶片上的输入/输出（I / O）焊盘阵列，使得测试仪通道可以同时与所有I / O焊盘通信。 互连结构包括实现总线节点阵列的电路板，每个总线节点对应于单独的一个I / O焊盘。 电路板包括至少两层。 安装在第一层上的轨迹形成一组第一个菊花链总线，每个链路总线连接总线节点阵列的单独行的所有总线节点。 安装在第二电路板层上的迹线形成一组第二菊花链总线，每条链路总线连接总线节点阵列的单独列的所有总线节点。 第一和第二菊花链总线的通路和其他电路板互连端，使得它们形成闭合栅格总线。 每个总线节点通过单独的隔离电阻器连接到安装在电路板表面上的单独的接触焊盘。 一组弹簧触点或探针将每个接触垫连接到晶片上的单独的I / O焊盘之间。

公开(公告)号：US20080303541A1

公开(公告)日：2008-12-11

申请号：US12194423

申请日：2008-08-19

申请人： Charles A. Miller

发明人： Charles A. Miller

IPC分类号： G01R1/073

CPC分类号： G01R31/2889 ,  G01R31/31905

摘要： A test system includes a communications channel that terminals in a probe, which contacts an input terminal of an electronic device to be tested. A resistor is connected between the communications channel near the probe and ground. The resistor reduces the input resistance of the terminal and thereby reduces the rise and fall times of the input terminal. The channel may be terminated in a branch having multiple paths in which each path is terminated with a probe for contacting a terminal on electronic devices to be tested. Isolation resistors are included in the branches to prevent a fault at one input terminal from propagating to the other input terminals. A shunt resistor is provided in each branch, which reduces the input resistance of the terminal and thereby reduces the rise and fall times of the input terminal. The shunt resistor may also be sized to reduce, minimize, or eliminate signal reflections back up the channel.

摘要翻译： 测试系统包括通信信道，探测器中的终端接触要测试的电子设备的输入端。 在探头和地之间的通信通道之间连接一个电阻。 该电阻降低了端子的输入电阻，从而减小了输入端子的上升和下降时间。 信道可以在具有多个路径的分支中终止，其中每个路径用用于接触待测试的电子设备上的终端的探针终止。 隔离电阻包括在分支中，以防止一个输入端子的故障传播到其他输入端子。 在每个分支中设置有分流电阻器，这降低了端子的输入电阻，从而减小了输入端子的上升和下降时间。 分流电阻器的尺寸也可以减小，最小化或消除信道反射信号的反射。

公开(公告)号：US07453258B2

公开(公告)日：2008-11-18

申请号：US10937470

申请日：2004-09-09

申请人： Charles A. Miller

发明人： Charles A. Miller

IPC分类号： G01R31/28

CPC分类号： G01R31/3008

摘要： A system is provided to enable leakage current measurement or parametric tests to be performed with an isolation buffer provided in a channel line. Multiple such isolation buffers are used to connect a single signal channel to multiple lines. Leakage current measurement is provided by providing a buffer bypass element, such as a resistor or transmission gate, between the input and output of each buffer. The buffer bypass element can be used to calibrate buffer delay out of the test system by using TDR measurements to determine the buffer delay based on reflected pulses through the buffer bypass element. Buffer delay can likewise be calibrated out by comparing measurements of a buffered and non-buffered channel line, or by measuring a device having a known delay.

摘要翻译： 提供了一种系统，用于使泄漏电流测量或参数测试能够与通道线中提供的隔离缓冲器一起进行。 多个这样的隔离缓冲器用于将单个信号通道连接到多条线路。 泄漏电流测量通过在每个缓冲器的输入和输出之间提供缓冲旁路元件（例如电阻器或传输门）来提供。 缓冲旁路元件可用于通过使用TDR测量来确定缓冲器延迟，以通过缓冲旁路元件反射的脉冲来校准测试系统中的缓冲延迟。 同样可以通过比较缓冲和非缓冲通道线的测量值，或通过测量具有已知延迟的器件来校准缓冲器延迟。

公开(公告)号：US20080191722A1

公开(公告)日：2008-08-14

申请号：US12107645

申请日：2008-04-22

申请人： Charles A. Miller

发明人： Charles A. Miller

IPC分类号： G01R31/02

CPC分类号： H03H11/265 ,  G01R31/2889 ,  G01R31/31917 ,  H03H11/126

摘要： A system is provided for controlling the delay in an isolation buffer. Multiple such isolation buffers are used to connect a single signal channel to multiple lines and controlled to provide an equal delay. Isolation buffer delay is controlled to be uniform by varying either power supply voltage or current. A single delay control circuit forming a delay-lock loop supplies the delay control signal to each buffet to assure the uniform delay. Since controlling delay can also vary the output voltage of each isolation buffer, in one embodiment buffers are made from two series inverters: one with a variable delay, and the second without a variable delay providing a fixed output voltage swing. To reduce circuitry needed, in one embodiment an isolation buffer with a variable power supply is provided in a channel prior to a branch, while buffers having a fixed delay are provided in each branch. A wafer test system can be configured using the isolation buffers having equal delays to enable concurrently connecting one tester channel to multiple wafer test probes.

摘要翻译： 提供了一种用于控制隔离缓冲器中的延迟的系统。 多个这样的隔离缓冲器用于将单个信号信道连接到多个线路并被控制以提供相等的延迟。 通过改变电源电压或电流来将隔离缓冲器延迟控制为均匀。 形成延迟锁定环的单个延迟控制电路将延迟控制信号提供给每个自助餐以确保均匀的延迟。 由于控制延迟也可以改变每个隔离缓冲器的输出电压，在一个实施例中，缓冲器由两个串联的反相器制成：一个具有可变延迟，第二个不具有可变延迟，提供固定的输出电压摆幅。 为了减少所需的电路，在一个实施例中，在分支之前的通道中提供具有可变电源的隔离缓冲器，而在每个分支中提供具有固定延迟的缓冲器。 可以使用具有相等延迟的隔离缓冲器来配置晶片测试系统，以使得能够将一个测试仪通道同时连接到多个晶片测试探针。

公开(公告)号：US07362092B2

公开(公告)日：2008-04-22

申请号：US11615976

申请日：2006-12-24

申请人： Charles A. Miller

发明人： Charles A. Miller

IPC分类号： G01R31/00

CPC分类号： H03H11/265 ,  G01R31/2889 ,  G01R31/31917 ,  H03H11/126

摘要： A system is provided for controlling the delay in an isolation buffer. Multiple such isolation buffers are used to connect a single signal channel to multiple lines and controlled to provide an equal delay. Isolation buffer delay is controlled to be uniform by varying either power supply voltage or current. A single delay control circuit forming a delay-lock loop supplies the delay control signal to each buffer to assure the uniform delay. Since controlling delay can also vary the output voltage of each isolation buffer, in one embodiment buffers are made from two series inverters: one with a variable delay, and the second without a variable delay providing a fixed output voltage swing. To reduce circuitry needed, in one embodiment an isolation buffer with a variable power supply is provided in a channel prior to a branch, while buffers having a fixed delay are provided in each branch. A wafer test system can be configured using the isolation buffers having equal delays to enable concurrently connecting one tester channel to multiple wafer test probes.

摘要翻译： 提供了一种用于控制隔离缓冲器中的延迟的系统。 多个这样的隔离缓冲器用于将单个信号信道连接到多个线路并被控制以提供相等的延迟。 通过改变电源电压或电流来将隔离缓冲器延迟控制为均匀。 形成延迟锁定环的单个延迟控制电路将延迟控制信号提供给每个缓冲器，以确保均匀延迟。 由于控制延迟也可以改变每个隔离缓冲器的输出电压，在一个实施例中，缓冲器由两个串联的反相器制成：一个具有可变延迟，第二个不具有可变延迟，提供固定的输出电压摆幅。 为了减少所需的电路，在一个实施例中，在分支之前的通道中提供具有可变电源的隔离缓冲器，而在每个分支中提供具有固定延迟的缓冲器。 可以使用具有相等延迟的隔离缓冲器来配置晶片测试系统，以使得能够将一个测试仪通道同时连接到多个晶片测试探针。

公开(公告)号：US07307433B2

公开(公告)日：2007-12-11

申请号：US10828755

申请日：2004-04-21

申请人： Charles A. Miller ,  Matthew E. Chraft ,  Roy J. Henson

发明人： Charles A. Miller ,  Matthew E. Chraft ,  Roy J. Henson

IPC分类号： G01R31/02 ,  G01R31/06

CPC分类号： G01R31/31905 ,  G01R1/07385 ,  G01R1/36 ,  G01R31/2889 ,  G01R35/00

摘要： A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs; (c) self test provided using an on board micro-controller or FPGA; (d) stacked daughter cards provided as part of the probe card to accommodate the additional on board test circuitry; and (e) use of a interface bus between a base PCB and daughter cards of the probe card, or the test system controller to minimize the number of interface wires between the base PCB and daughter cards or between the base PCB and the test system controller.

摘要翻译： 用于晶片测试系统的探针卡具有多个板上特征，使扇出测试系统控制器通道以测试晶片上的多个DUT，同时限制扇出对测试结果的不期望的影响。 探头卡的板载功能包括以下一个或多个功能：（a）通过将电阻器与每个DUT输入串联放置来隔离故障DUT提供的DUT信号隔离; （b）与每个DUT电源引脚串联的开关，限流器或稳压器提供的DUT电源隔离，以将电源与失效的DUT隔离; （c）使用板载微控制器或FPGA提供的自检; （d）作为探针卡的一部分提供的堆叠子卡，以适应额外的板上测试电路; 和（e）在基板PCB和探针卡的子卡之间使用接口总线或测试系统控制器以最小化基板PCB和子卡之间或基板和测试系统控制器之间的接口线的数量 。