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公开(公告)号：US07339390B2
公开(公告)日：2008-03-04
申请号：US11140765
申请日：2005-05-31
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.
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公开(公告)号：US06828232B2
公开(公告)日：2004-12-07
申请号：US10705116
申请日：2003-11-10
IPC分类号： H01L214763
CPC分类号： H01L28/20 , H01L27/0688
摘要： An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.
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63.发明授权Hierarchical power supply noise monitoring device and system for very large scale integrated circuits 有权用于大型集成电路的分层电源噪声监测装置和系统公开(公告)号：US06823293B2
公开(公告)日：2004-11-23
申请号：US10334312
申请日：2002-12-31
申请人： Howard H. Chen , Louis Lu-Chen Hsu , Brian L. Ji , Li-Kong Wang
发明人： Howard H. Chen , Louis Lu-Chen Hsu , Brian L. Ji , Li-Kong Wang
IPC分类号： G06F1500
CPC分类号： G01R31/3004 , G01R31/31721
摘要： A hierarchical power supply noise monitoring device and system for very large scale integrated circuits. The noise-monitoring device is fabricated on-chip to measure the noise on the chip. The noise-monitoring system includes a plurality of on-chip noise-monitoring devices distributed strategically across the chip. A noise-analysis algorithm analyzes the noise characteristics from the noise data collected from the noise-monitoring devices, and a hierarchical noise-monitoring system maps the noise of each core to the system on chip.
摘要翻译： 一种用于大规模集成电路的分层电源噪声监测装置和系统。 噪声监测装置是片上制造的，以测量芯片上的噪声。 噪声监测系统包括跨芯片战略性分布的多个片上噪声监测装置。 噪声分析算法从噪声监测装置收集的噪声数据中分析噪声特性，分层噪声监测系统将每个核心的噪声映射到片上系统。
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公开(公告)号：US06552378B1
公开(公告)日：2003-04-22
申请号：US09385931
申请日：1999-08-30
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10832 , H01L27/10873
摘要： A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic dimension. The semiconductor memory cell includes a storage capacitor formed in a trench, a transfer device formed in a substantially electrically isolated mesa region extending over a substantial arc of the outer perimeter of the trench, a buried strap which conductively connects the transfer device to the storage capacitor, wherein the transfer device has a controlled conduction channel located at a position of the arc removed from the buried strap.
摘要翻译： 本文公开了一种具有4.5F2或更小尺寸的半导体存储器单元的制造结构和方法，其中F是最小光刻尺寸。 半导体存储单元包括形成在沟槽中的存储电容器，形成在基本上电隔离的台面区域中的转移装置，该台面区域延伸在沟槽的外周边的大致圆弧上，将传输装置导电地连接到存储电容器 ，其中所述传送装置具有位于从所述掩埋带移除的所述弧的位置处的受控传导通道。
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65.发明授权N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same 失效N沟道金属氧化物半导体（NMOS）驱动电路及其制造方法公开(公告)号：US06433397B1
公开(公告)日：2002-08-13
申请号：US09488515
申请日：2000-01-21
IPC分类号： H01L27085
CPC分类号： H01L29/6659 , H01L21/2251 , H01L21/76895 , H01L27/088 , Y10S438/969
摘要： An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration N-type implantation, and an N-driver coupled to the boost gate stack.
摘要翻译： N沟道金属氧化物半导体（NMOS）驱动电路（及其制造方法）包括形成在基板上的升压栅叠层，具有通过低浓度N型注入形成的源极和漏极，以及N- 驱动器耦合到升压栅极堆叠。
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公开(公告)号：US06426903B1
公开(公告)日：2002-07-30
申请号：US09923721
申请日：2001-08-07
IPC分类号： G11C700
CPC分类号： G11C29/80 , Y10S977/888 , Y10S977/943
摘要： A static redundancy arrangement for a circuit using a focused ion beam anti-fuse methodology which reduces the circuit layout area and the switching activity compared to a prior art dynamic redundancy scheme, resulting in less power, a simpler design and higher speed. Focused ion beam anti-fuse methodology is used to program redundancy for circuits, particularly wide I/O embedded DRAM macros. An anti-fuse array circuit is comprised of a plurality of anti-fuse programming elements, each of which comprises a latch circuit controlled by a set input signal, and an anti-fuse device which is programmed by a focused ion beam.
摘要翻译： 使用聚焦离子束反熔丝方法的电路的静态冗余布置，与现有技术的动态冗余方案相比，其减小了电路布局面积和开关活动，导致较少的功率，更简单的设计和更高的速度。 聚焦离子束反熔丝方法用于编程电路冗余，特别是宽I / O嵌入式DRAM宏。 反熔丝阵列电路由多个反熔丝编程元件组成，每个反熔丝编程元件包括由设定的输入信号控制的锁存电路和由聚焦离子束编程的反熔丝器件。
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公开(公告)号：US06343044B1
公开(公告)日：2002-01-29
申请号：US09679124
申请日：2000-10-04
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C5/146 , G11C8/08 , G11C11/4074 , G11C2207/104
摘要： A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.
摘要翻译： 用于实现Vbb（阵列体偏置）和Vwl（负字线）电压发生器的存储电路中的功耗的显着降低的系统和方法。 该系统包括在睡眠或待机模式期间关闭负WL发生器，使得不消耗电力。 执行松弛的刷新操作，负的WL由Vbb发生器供电。 由于联合Vbb-Vwl去耦方案，耦合到BL摆幅的负WL电源的噪声减小。 在活动模式下，Vbb和Vneg被分离，以避免任何交叉噪声并保持设计灵活性。 在上电期间，Vwl发生器提高了Vbb电平的上升速率。 其优点可概括为：（1）Vbb发电机设计更简单，（2）Vbb发电机尺寸小得多，（3）Vbb功率降低，（4）Vwl发电机无待机电流，（5）低去耦噪声 待机或休眠模式下的Vwl电平，（6）上电期间Vbb的提升速率，（7）在活动模式期间Vbb和Vwl之间没有交叉噪声，（8）Vbb和Vbb的设计灵活性 Vwl处于活动模式。 本发明的原理和优点可以应用于任何两个或多个DC发电机系统，负极或正极。
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68.发明授权Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure 有权用于形成在一个衬底上包括NVRAM，DRAM和/或SRAM存储器结构的存储器结构的工艺以及用于形成新的NVRAM单元结构的工艺公开(公告)号：US06232173B1
公开(公告)日：2001-05-15
申请号：US09159470
申请日：1998-09-23
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , G11C11/005 , H01L27/105 , H01L27/10808 , H01L27/10852 , H01L27/115 , H01L27/11517 , H01L27/11526
摘要： A semiconductor memory device including an NVRAM cell structure, a DRAM cell structure, and an SRAM cell structure. The NVRAM cell structure, the DRAM cell structure, and the SRAM cell structure are on the same substrate. An NVRAM cell structure. Processes for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and processes for forming a new NVRAM cell structure.
摘要翻译： 一种包括NVRAM单元结构，DRAM单元结构和SRAM单元结构的半导体存储器件。 NVRAM单元结构，DRAM单元结构和SRAM单元结构位于相同的基板上。 NVRAM单元结构。 用于形成在一个衬底上包括NVRAM，DRAM和/或SRAM存储器结构并且用于形成新的NVRAM单元结构的处理的存储器结构的过程。
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公开(公告)号：US5910912A
公开(公告)日：1999-06-08
申请号：US968736
申请日：1992-10-30
申请人： Louis Lu-Chen Hsu , Chang-Ming Hsieh , Seiki Ogura
发明人： Louis Lu-Chen Hsu , Chang-Ming Hsieh , Seiki Ogura
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , G11C16/0425 , H01L21/2815 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly sidewalls of an aperture in which the select gate is formed, so that the final structure has dimensions that are less than those obtainable with optical lithography because both gates are sidewalls and therefore not limited to the dimensions achievable with optical lithography.
摘要翻译： EEPROM单元包括具有用于存储数据的浮动栅极和访问单元的选择栅极的双栅极晶体管，每个栅极均由多边形成，并由通过生长氧化物形成的薄垂直氧化物元件分隔开 在其中形成选择栅极的孔径的垂直多边形上，使得最终结构的尺寸小于通过光学光刻获得的尺寸，因为两个栅极都是侧壁，因此不限于光学光刻实现的尺寸。
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70.发明授权Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure 失效低成本混合内存集成结构，新的NVRAM结构，以及形成混合内存和NVRAM结构的过程
公开(公告)号：US5880991A
公开(公告)日：1999-03-09
申请号：US824702
申请日：1997-04-14
IPC分类号： G11C11/00 , H01L21/8242 , H01L21/8244 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： H01L27/10894 , G11C11/005 , H01L27/105 , H01L27/10808 , H01L27/115 , H01L27/11517 , H01L27/11526 , H01L27/10852
摘要： A semiconductor memory device including an NVRAM cell structure, a DRAM cell structure, and an SRAM cell structure. The NVRAM cell structure, the DRAM cell structure, and the SRAM cell structure are on the same substrate. An NVRAM cell structure. Processes for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and processes for forming a new NVRAM cell structure.
摘要翻译： 一种包括NVRAM单元结构，DRAM单元结构和SRAM单元结构的半导体存储器件。 NVRAM单元结构，DRAM单元结构和SRAM单元结构位于相同的基板上。 NVRAM单元结构。 用于形成在一个衬底上包括NVRAM，DRAM和/或SRAM存储器结构并且用于形成新的NVRAM单元结构的处理的存储器结构的过程。
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