公开(公告)号：US09698280B2

公开(公告)日：2017-07-04

申请号：US15062268

申请日：2016-03-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Motomu Kurata ,  Kazuya Hanaoka ,  Yoshiyuki Kobayashi ,  Daisuke Matsubayashi

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/04 ,  H01L29/24

Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section.

公开(公告)号：US20160141422A1

公开(公告)日：2016-05-19

申请号：US15001300

申请日：2016-01-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daisuke Matsubayashi ,  Satoshi Shinohara ,  Wataru Sekine

IPC: H01L29/786 ,  H01L29/49

CPC classification number: H01L29/7869 ,  H01L29/4908 ,  H01L29/78612 ,  H01L29/78696

Abstract: A semiconductor device in which deterioration of electrical characteristics which becomes more noticeable as the transistor is miniaturized can be suppressed is provided. The semiconductor device includes an oxide semiconductor stack in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are stacked in this order from the substrate side over a substrate; a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor stack; a gate insulating film over the oxide semiconductor stack, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating film. The first oxide semiconductor layer includes a first region. The gate insulating film includes a second region. When the thickness of the first region is TS1 and the thickness of the second region is TG1, TS1≧TG1.

Abstract translation: 提供了可以抑制由于晶体管小型化而变得更显着的电特性劣化的半导体器件。 半导体器件包括氧化物半导体堆叠，其中第一氧化物半导体层，第二氧化物半导体层和第三氧化物半导体层从衬底侧依次层叠在衬底上; 与氧化物半导体堆叠接触的源电极层和漏电极层; 氧化物半导体堆叠上的栅极绝缘膜，源极电极层和漏极电极层; 以及栅极绝缘膜上的栅极电极层。 第一氧化物半导体层包括第一区域。 栅极绝缘膜包括第二区域。 当第一区域的厚度为TS1且第二区域的厚度为TG1时，TS1≥TG1。

公开(公告)号：US09287411B2

公开(公告)日：2016-03-15

申请号：US14061510

申请日：2013-10-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichi Koezuka ,  Yukinori Shima ,  Hajime Tokunaga ,  Toshinari Sasaki ,  Keisuke Murayama ,  Daisuke Matsubayashi

IPC: H01L21/00 ,  H01L29/786 ,  H01L21/02 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/022 ,  H01L21/02263 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L29/24 ,  H01L29/513 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78693

Abstract: In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide semiconductor film has an amorphous structure or a microcrystalline structure, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.

Abstract translation: 在包括晶体管的半导体器件中，所述晶体管包括形成在衬底上的栅电极，覆盖栅电极的栅极绝缘膜，与栅电极重叠的多层膜，栅极绝缘膜设置在其间;以及一对电极， 多层膜，覆盖晶体管的第一氧化物绝缘膜和形成在第一氧化物绝缘膜上的第二氧化物绝缘膜，所述多层膜包括氧化物半导体膜和含有In或Ga的氧化物膜，所述氧化物半导体膜具有无定形 结构或微晶结构，所述第一氧化物绝缘膜是透过氧的氧化物绝缘膜，所述第二氧化物绝缘膜是比所述化学计量组成中含有氧更多的氧化物绝缘膜。

公开(公告)号：US09252283B2

公开(公告)日：2016-02-02

申请号：US14093648

申请日：2013-12-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daisuke Matsubayashi ,  Satoshi Shinohara ,  Wataru Sekine

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/4908 ,  H01L29/78612 ,  H01L29/78696

Abstract: A semiconductor device in which deterioration of electrical characteristics which becomes more noticeable as the transistor is miniaturized can be suppressed is provided. The semiconductor device includes an oxide semiconductor stack in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are stacked in this order from the substrate side over a substrate; a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor stack; a gate insulating film over the oxide semiconductor stack, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating film. The first oxide semiconductor layer includes a first region. The gate insulating film includes a second region. When the thickness of the first region is TS1 and the thickness of the second region is TG1, TS1≧TG1.

Abstract translation: 提供了可以抑制由于晶体管小型化而变得更显着的电特性劣化的半导体器件。 半导体器件包括氧化物半导体堆叠，其中第一氧化物半导体层，第二氧化物半导体层和第三氧化物半导体层从衬底侧依次层叠在衬底上; 与氧化物半导体堆叠接触的源电极层和漏电极层; 氧化物半导体堆叠上的栅极绝缘膜，源极电极层和漏极电极层; 以及栅极绝缘膜上的栅极电极层。 第一氧化物半导体层包括第一区域。 栅极绝缘膜包括第二区域。 当第一区域的厚度为TS1且第二区域的厚度为TG1时，TS1≥TG1。

公开(公告)号：US09130047B2

公开(公告)日：2015-09-08

申请号：US14338575

申请日：2014-07-23

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masayuki Sakakura ,  Daisuke Matsubayashi ,  Yoshiyuki Kobayashi

IPC: H01L29/78 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/66742 ,  H01L29/7831 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78684

Abstract: A semiconductor device with a transistor in which current flowing between a source and a drain when the voltage of a gate electrode is 0 V can be reduced is provided. The semiconductor device incorporates a multi-gate transistor having an oxide semiconductor film formed over an insulating surface, a first gate insulating film in contact with a first surface of the oxide semiconductor film, a first gate electrode between the insulating surface and the oxide semiconductor film, a second gate insulating film in contact with a second surface of the oxide semiconductor film, and a second gate electrode in contact with the second gate insulating film. The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region not overlapping with the first gate electrode, and the second gate electrode overlaps with the first region and the second region of the oxide semiconductor film.

Abstract translation: 提供具有晶体管的半导体器件，其中当栅电极的电压为0V时，在源极和漏极之间流动的电流可以被减小。 半导体器件包括：多栅极晶体管，其具有在绝缘表面上形成的氧化物半导体膜，与氧化物半导体膜的第一表面接触的第一栅极绝缘膜，绝缘表面和氧化物半导体膜之间的第一栅电极 与氧化物半导体膜的第二表面接触的第二栅极绝缘膜和与第二栅极绝缘膜接触的第二栅电极。 氧化物半导体膜具有与第一栅电极重叠的第一区域和与第一栅电极不重叠的第二区域，第二栅电极与氧化物半导体膜的第一区域和第二区域重叠。

公开(公告)号：US20150214378A1

公开(公告)日：2015-07-30

申请号：US14603632

申请日：2015-01-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daisuke Matsubayashi ,  Yoshiyuki Kobayashi ,  Shuhei Nagatsuka ,  Yutaka Shionoiri

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78648 ,  H01L29/78696

Abstract: A transistor having favorable electrical characteristics. A transistor suitable for miniaturization. A transistor having a high switching speed. One embodiment of the present invention is a semiconductor device that includes a transistor. The transistor includes an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor includes a first region in which the oxide semiconductor and the gate electrode overlap with each other with the gate insulator positioned therebetween. The transistor has a threshold voltage higher than 0 V and a switching speed lower than 100 nanoseconds.

Abstract translation: 具有良好电特性的晶体管。 适合小型化的晶体管。 具有高切换速度的晶体管。 本发明的一个实施例是包括晶体管的半导体器件。 晶体管包括氧化物半导体，栅电极和栅极绝缘体。 氧化物半导体包括第一区域，其中氧化物半导体和栅电极彼此重叠，栅极绝缘体位于它们之间。 晶体管的阈值电压高于0V，开关速度低于100纳秒。

公开(公告)号：US08969867B2

公开(公告)日：2015-03-03

申请号：US13738443

申请日：2013-01-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Daisuke Matsubayashi ,  Yutaka Okazaki

IPC: H01L29/12 ,  H01L27/12 ,  H01L21/84 ,  H01L29/786 ,  H01L29/78

CPC classification number: H01L29/7869 ,  H01L29/785 ,  H01L29/78609 ,  H01L29/78696

Abstract: The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less). Alternatively, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the resistivity of the source region and the drain region is 1.9×10−5 Ω·m or more and 4.8×10−3 Ω·m or less.

Abstract translation: 半导体器件包括具有沟道形成区域的氧化物半导体膜，栅极绝缘膜和栅极电极层的晶体管。 在晶体管中，沟道长度小（5nm以上且小于60nm，优选为10nm以上且40nm以下），栅极绝缘膜的厚度大（通过以下方式获得的等效氧化物厚度 转化成含有氮的氧化硅的厚度为5nm以上且50nm以下，优选为10nm以上至40nm以下。 或者，通道长度小（5nm以上且小于60nm，优选为10nm以上且40nm以下），源极区域和漏极区域的电阻率为1.9×10-5＆OHgr· m以上4.8×10-3＆OHgr·m以下。

公开(公告)号：US20150034945A1

公开(公告)日：2015-02-05

申请号：US14338575

申请日：2014-07-23

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masayuki Sakakura ,  Daisuke Matsubayashi ,  Yoshiyuki Kobayashi

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/66742 ,  H01L29/7831 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78684

Abstract: A semiconductor device with a transistor in which current flowing between a source and a drain when the voltage of a gate electrode is 0 V can be reduced is provided. The semiconductor device incorporates a multi-gate transistor having an oxide semiconductor film formed over an insulating surface, a first gate insulating film in contact with a first surface of the oxide semiconductor film, a first gate electrode between the insulating surface and the oxide semiconductor film, a second gate insulating film in contact with a second surface of the oxide semiconductor film, and a second gate electrode in contact with the second gate insulating film. The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region not overlapping with the first gate electrode, and the second gate electrode overlaps with the first region and the second region of the oxide semiconductor film.

Abstract translation: 提供具有晶体管的半导体器件，其中当栅电极的电压为0V时，在源极和漏极之间流动的电流可以被减小。 半导体器件包括：多栅极晶体管，其具有在绝缘表面上形成的氧化物半导体膜，与氧化物半导体膜的第一表面接触的第一栅极绝缘膜，绝缘表面和氧化物半导体膜之间的第一栅电极 与氧化物半导体膜的第二表面接触的第二栅极绝缘膜和与第二栅极绝缘膜接触的第二栅电极。 氧化物半导体膜具有与第一栅电极重叠的第一区域和与第一栅电极不重叠的第二区域，第二栅电极与氧化物半导体膜的第一区域和第二区域重叠。

公开(公告)号：US12148835B2

公开(公告)日：2024-11-19

申请号：US18211652

申请日：2023-06-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Tetsuhiro Tanaka ,  Hirokazu Watanabe ,  Yuhei Sato ,  Yasumasa Yamane ,  Daisuke Matsubayashi

IPC: H01L29/786 ,  H01L29/45 ,  H01L29/66

Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.

公开(公告)号：US12063798B2

公开(公告)日：2024-08-13

申请号：US18203736

申请日：2023-05-31

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takanori Matsuzaki ,  Yoshinobu Asami ,  Daisuke Matsubayashi ,  Tatsuya Onuki

IPC: H01L27/12 ,  H01L29/786 ,  H10B99/00

CPC classification number: H10B99/00 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1244 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.