公开(公告)号：US09607991B2

公开(公告)日：2017-03-28

申请号：US14471151

申请日：2014-08-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takeshi Aoki

IPC: H01L27/108 ,  H01L27/12 ,  H01L27/1156

CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00012

Abstract: To provide a semiconductor memory device which can be manufactured with high yield and which can achieve higher integration. A pair of memory cells adjacent to each other in the bit line direction is connected to a bit line through a common contact hole. The pair of memory cells adjacent to each other in the bit line direction shares an electrode connected to the bit line. An oxide semiconductor layer included in the memory cell is provided to overlap with a word line and a capacitor line. A transistor and a capacitor included in the memory cell are each provided to overlap with the bit line connected to the memory cell.

公开(公告)号：US09461646B2

公开(公告)日：2016-10-04

申请号：US15007350

申请日：2016-01-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Kozuma ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Takeshi Aoki ,  Yuki Okamoto

IPC: H03K19/177 ,  H03K19/00 ,  H03K19/0948

CPC classification number: H03K19/0013 ,  H03K19/0948 ,  H03K19/17728 ,  H03K19/1776

Abstract: A semiconductor device suitable for low-voltage driving. The semiconductor device includes a first transistor, a second transistor, a power supply line, a circuit, and a memory circuit. The first transistor controls electrical continuity between the circuit and the power supply line. The memory circuit stores data for setting a gate potential of the first transistor. The second transistor controls electrical continuity between an output node of the memory circuit and a gate of the first transistor. The second transistor is a transistor with an ultralow off-state current, for example, an oxide semiconductor transistor. In a period for operating the circuit, a first potential is input to the power supply line and the second transistor is turned off. In a period for updating the gate potential of the first transistor, a second potential is input to the power supply line. The second potential is higher than the first potential.

Abstract translation: 适用于低压驱动的半导体器件。 半导体器件包括第一晶体管，第二晶体管，电源线，电路和存储器电路。 第一个晶体管控制电路和电源线之间的电气连续性。 存储电路存储用于设置第一晶体管的栅极电位的数据。 第二晶体管控制存储电路的输出节点和第一晶体管的栅极之间的电连续性。 第二晶体管是具有超低截止电流的晶体管，例如氧化物半导体晶体管。 在用于操作电路的时段中，第一电位被输入到电源线并且第二晶体管被截止。 在用于更新第一晶体管的栅极电位的时段中，第二电位被输入到电源线。 第二个潜力高于第一个潜力。

公开(公告)号：US09401364B2

公开(公告)日：2016-07-26

申请号：US14856097

申请日：2015-09-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Munehiro Kozuma ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Takeshi Aoki

IPC: H01L29/10 ,  H01L27/11 ,  H01L29/786

CPC classification number: H01L27/11 ,  G11C11/24 ,  G11C14/0009 ,  H01L27/10814 ,  H01L29/7869

Abstract: A semiconductor device has a function of storing data and includes an output terminal, a first terminal, a second terminal, a first circuit, and second circuits. The first circuit has a function of keeping the potential of the output terminal to be a high-level or low-level potential. The second circuits each include a first pass transistor and a second pass transistor which are electrically connected in series, a first memory circuit, and a second memory circuit. The first and second memory circuits each have a function of making a potential retention node in an electrically floating state. The potential retention nodes of the first and second memory circuits are electrically connected to gates of the first and second pass transistors, respectively. A transistor including an oxide semiconductor layer may be provided in the first and second memory circuits.

Abstract translation: 半导体器件具有存储数据的功能，并且包括输出端子，第一端子，第二端子，第一电路和第二电路。 第一电路具有将输出端子的电位保持为高电平或低电位的功能。 第二电路各自包括串联电连接的第一传输晶体管和第二传输晶体管，第一存储器电路和第二存储器电路。 第一和第二存储器电路各自具有使电位保持节点处于电浮动状态的功能。 第一和第二存储器电路的电势保持节点分别电连接到第一和第二传输晶体管的栅极。 包括氧化物半导体层的晶体管可以设置在第一和第二存储器电路中。

公开(公告)号：US20160118426A1

公开(公告)日：2016-04-28

申请号：US14986119

申请日：2015-12-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Hikaru Tamura ,  Munehiro Kozuma ,  Masataka Ikeda ,  Takeshi Aoki

IPC: H01L27/146 ,  H01L31/105 ,  H01L29/786

CPC classification number: H01L27/14616 ,  H01L27/14603 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14643 ,  H01L29/7869 ,  H01L31/1055 ,  H04N5/361 ,  H04N5/374 ,  H04N5/378

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

公开(公告)号：US09225336B2

公开(公告)日：2015-12-29

申请号：US14587588

申请日：2014-12-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi Aoki ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Munehiro Kozuma

IPC: H03K19/177 ,  H03K19/0175

CPC classification number: H03K19/1776 ,  H03K19/017581

Abstract: To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed.

公开(公告)号：US09111836B2

公开(公告)日：2015-08-18

申请号：US14583363

申请日：2014-12-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Munehiro Kozuma ,  Takeshi Aoki

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  G01J1/44 ,  H01L27/14609 ,  H04N5/378

Abstract: A semiconductor device includes a photodiode, a first transistor, a second transistor, and a third transistor. The second transistor and the third transistor have a function of retaining a charge accumulated in a gate of the first transistor. In a period during which the second transistor and the third transistor are off, a voltage level of a voltage applied to a gate of the second transistor is set to be lower than a voltage level of a source of the second transistor and a voltage level of a drain of the second transistor, and a voltage level of a voltage applied to a gate of the third transistor is set to be lower than a voltage level of a source of the third transistor and a voltage level of a drain of the third transistor.

公开(公告)号：US09048832B2

公开(公告)日：2015-06-02

申请号：US14170825

申请日：2014-02-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Kozuma ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Takeshi Aoki

IPC: H03K19/177

CPC classification number: H03K19/0013 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/7869 ,  H03K19/09441 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17748 ,  H03K19/1776

Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.

Abstract translation: 可编程逻辑器件包括多个可编程逻辑元件（PLE），其电连接由第一配置数据控制。 每个PLE包括LUT，其中输入信号的逻辑电平和输出信号的逻辑电平之间的关系由第二配置数据确定，输入LUT的输出信号的FF和MUX 。 MUX包括至少两个开关，每个开关包括第一和第二晶体管。 包括第三配置数据的信号通过第一晶体管输入到第二晶体管的栅极。 LUT的输出信号或FF的输出信号被输入到第二晶体管的源极和漏极之一。

公开(公告)号：US20140368235A1

公开(公告)日：2014-12-18

申请号：US14305434

申请日：2014-06-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi Aoki ,  Yoshiyuki Kurokawa ,  Munehiro Kozuma ,  Takashi Nakagawa

IPC: H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/0013 ,  H03K19/018585

Abstract: Data of a register in a programmable logic element is retained. A volatile storage circuit and a nonvolatile storage circuit are provided in a register of a programmable logic element whose function can be changed in response to a plurality of context signals. The nonvolatile storage circuit includes nonvolatile storage portions for storing data in the register. The number of nonvolatile storage portions corresponds to the number of context signals. With such a structure, the function can be changed each time context signals are switched and data in the register that is changed when the function is changed can be backed up to the nonvolatile storage portion in each function. In addition, the function can be changed each time context signals are switched and the data in the register that is backed up when the function is changed can be recovered to the volatile storage circuit.

Abstract translation: 可编程逻辑元件中寄存器的数据被保留。 易失性存储电路和非易失性存储电路设置在可编程逻辑元件的寄存器中，该可编程逻辑元件的功能可以响应于多个上下文信号而改变。 非易失性存储电路包括用于将数据存储在寄存器中的非易失性存储部分。 非易失性存储部分的数量对应于上下文信号的数量。 通过这样的结构，可以在每次上下文信号切换时改变功能，并且在功能改变时改变的寄存器中的数据可以备份到每个功能中的非易失性存储部分。 此外，每当上下文信号被切换并且功能改变时备份的寄存器中的数据可以被恢复到易失性存储电路时，可以改变该功能。

公开(公告)号：US20140286076A1

公开(公告)日：2014-09-25

申请号：US14217793

申请日：2014-03-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takeshi Aoki ,  Yoshiyuki Kurokawa ,  Munehiro Kozuma

IPC: G11C5/06

CPC classification number: G11C5/06 ,  G11C7/1051 ,  G11C7/1057 ,  G11C11/24 ,  G11C14/0054

Abstract: A nonvolatile semiconductor device which can be driven at low voltage is provided. A nonvolatile semiconductor device with low power consumption is provided. A Schmitt trigger NAND circuit and a Schmitt trigger inverter are included. Data is held in a period when the supply of power supply voltage is continued, and a potential corresponding to the data is stored at a node electrically connected to a capacitor before a period when the supply of power supply voltage is stopped. By utilizing a change in channel resistance of a transistor whose gate is connected to the node, the data is restored in response to the restart of the supply of power supply voltage.

Abstract translation: 提供了可以以低电压驱动的非易失性半导体器件。 提供了具有低功耗的非易失性半导体器件。 包括施密特触发器NAND电路和施密特触发器反相器。 数据保持在电源电压继续供给的期间，与电源相对应的电位存储在与电容器电连接的节点上，在供给电源电压停止的期间。 通过利用其栅极连接到节点的晶体管的沟道电阻的变化，响应于电源电压的重新启动恢复数据。

公开(公告)号：US20140225644A1

公开(公告)日：2014-08-14

申请号：US14166936

申请日：2014-01-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi Aoki ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Munehiro Kozuma

IPC: H03K19/0175

CPC classification number: H03K19/1776 ,  H03K19/017581

Abstract: To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed.

Abstract translation: 提供具有减小的电路面积和增加的操作速度的PLD。 在电路结构中，设置在可编程开关元件的输入端子和输出端子之间的晶体管的栅极在信号被输入到可编程开关元件的时段内处于电浮动状态。 该结构使得能够响应于从可编程逻辑元件提供的信号的升压效应来增加栅极的电压，从而抑制幅度电压的降低。 这可以通过诸如上拉电路的升压电路占据的区域来减小电路面积，并且增加操作速度。