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    Method for the formation of fin structures for FinFET devices
    61.
    发明授权
    Method for the formation of fin structures for FinFET devices 有权
    用于形成FinFET器件鳍片结构的方法

    公开(公告)号：US08975168B2

    公开(公告)日：2015-03-10

    申请号：US13903630

    申请日：2013-05-28

    Applicant: STMicroelectronics, Inc.

    Inventor： Qing Liu ,  Nicolas Loubet

    IPC: H01L21/20 ,  H01L21/36 ,  H01L21/00 ,  H01L21/02

    CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/823821 ,  H01L21/845

    Abstract: A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made to cover the bottom portion. Germanium is then driven from the epitaxially grown silicon-germanium material into the bottom portion to convert the bottom portion to silicon-germanium. Further silicon-germanium growth is performed to define a silicon-germanium region in the second region adjacent the silicon region in the first region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type.

    Abstract translation: 由硅半导体材料形成的SOI衬底层包括相邻的第一和第二区域。 去除第二区域中的硅衬底层的一部分，使得第二区域保持由硅半导体材料制成的底部。 制造硅 - 锗半导体材料的外延生长以覆盖底部。 然后将锗从外延生长的硅 - 锗材料驱动到底部，以将底部部​​分转化为硅 - 锗。 执行进一步的硅 - 锗生长以在与第一区域中的硅区域相邻的第二区域中限定硅 - 锗区域。 图案化硅区域以限定第一（例如，n沟道）导电类型的FinFET的第一鳍结构。 硅 - 锗区域也被图案化以限定第二（例如p沟道）导电类型的FinFET的第二鳍结构。

    METHOD OF MAKING A SEMICONDUCTOR DEVICE INCLUDING AN ALL AROUND GATE
    63.
    发明申请
    METHOD OF MAKING A SEMICONDUCTOR DEVICE INCLUDING AN ALL AROUND GATE 有权
    制造包括所有边界的半导体器件的方法

    公开(公告)号：US20140357036A1

    公开(公告)日：2014-12-04

    申请号：US13906702

    申请日：2013-05-31

    Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Nicolas Loubet ,  Prasanna Khare ,  Huiming Bu

    IPC: H01L29/66

    CPC classification number: H01L29/66484 ,  H01L21/823481 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

    Abstract: A method of making a semiconductor device includes forming an intermediate structure including second semiconductor fin portions above a first semiconductor layer, and top first semiconductor fin portions extending from respective ones of the second semiconductor fin portions. The second semiconductor fin portions are selectively etchable with respect to the top first semiconductor fin portions. A dummy gate is on the intermediate structure. The second semiconductor fin portions are selectively etched to define bottom openings under respective ones of the top first semiconductor fin portions. The bottom openings are filled with a dielectric material.

    Abstract translation: 制造半导体器件的方法包括在第一半导体层之上形成包括第二半导体鳍部的中间结构以及从第二半导体鳍部中的相应半导体鳍部延伸的顶部第一半导体鳍部。 第二半导体鳍片部分相对于顶部第一半导体鳍片部分可选择性地蚀刻。 虚拟门在中间结构上。 选择性地蚀刻第二半导体鳍片部分以在顶部第一半导体鳍片部分的相应一个下限定底部开口。 底部开口填充有电介质材料。

    SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL EPITAXIAL SILICON-GERMANIUM REGION
    64.
    发明申请
    SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL EPITAXIAL SILICON-GERMANIUM REGION 有权
    具有通道外延硅 - 锗原子的无硅晶体管半导体结构

    公开(公告)号：US20140353718A1

    公开(公告)日：2014-12-04

    申请号：US13907460

    申请日：2013-05-31

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

    Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare ,  Stephane Allegret-Maret ,  Bruce Doris ,  Kangguo Cheng

    IPC: H01L29/786 ,  H01L27/092 ,  H01L27/11 ,  H01L29/66

    CPC classification number: H01L29/66772 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/78654

    Abstract: An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.

    Abstract translation: 一种具有沟道外延硅的改进的晶体管及其制造方法。 一方面，一种用于制造晶体管的方法包括：在外延硅区域上形成栅极叠层结构，外延硅区域的宽度尺寸近似于栅极堆叠结构的宽度尺寸; 将所述外延硅区域封装在所述栅极堆叠结构之下，并且在所述栅极堆叠结构和所述外延硅区域的两侧上形成牺牲间隔物; 形成晶体管的沟道，其宽度尺寸近似于形成在晶体管的沟道上的外延硅区域和栅极堆叠结构，外延硅区域和栅极堆叠结构; 去除牺牲隔离物; 并且从硅衬底生长隆起的外延源和漏极，其中凸起的外延源和漏极的一部分与外延硅区接触。

    LAYER FORMATION WITH REDUCED CHANNEL LOSS
    65.
    发明申请
    LAYER FORMATION WITH REDUCED CHANNEL LOSS 有权
    具有减少通道损失的层形成

    公开(公告)号：US20140299880A1

    公开(公告)日：2014-10-09

    申请号：US14309409

    申请日：2014-06-19

    Applicant: STMicroelectronics, Inc.

    Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare

    IPC: H01L29/10 ,  H01L29/04 ,  H01L29/78

    CPC classification number: H01L29/1033 ,  H01L29/04 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78

    Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.

    Abstract translation: 可以在半导体器件区域上形成绝缘层，并以基本上减少或防止下面的沟道区域的蚀刻量的方式进行蚀刻。 可以在栅极区域和半导体器件区域上形成第一绝缘层。 可以在第一绝缘层上形成第二绝缘层。 可以在第二绝缘层上形成第三绝缘层。 可以使用第一蚀刻工艺蚀刻第三绝缘层的一部分。 可以使用与第一蚀刻工艺不同的至少第二蚀刻工艺来蚀刻第三绝缘层的蚀刻部分下方的第一绝缘层和第二绝缘层的一部分。

    FACET-FREE STRAINED SILICON TRANSISTOR
    66.
    发明申请
    FACET-FREE STRAINED SILICON TRANSISTOR 审中-公开
    无菌无菌应变硅晶体管

    公开(公告)号：US20140151759A1

    公开(公告)日：2014-06-05

    申请号：US13692632

    申请日：2012-12-03

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

    IPC: H01L29/78 ,  H01L29/06 ,  H01L21/20 ,  H01L29/66

    CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/06 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.

    Abstract translation: 在外延生长的晶体中存在小面或空隙，表明晶体生长已被缺陷或某些材料边界中断。 在形成应变硅晶体管的源极和漏极区域的硅化合物的外延生长期间，可以抑制刻面。 已经观察到，当某些硅化合物的外延层相邻于氧化物边界生长时，可以发生刻面，但是当外延层生长在邻近硅边界或与氮化物边界相邻时，不会发生刻面。 因为硅化合物的外延生长通常在填充有氧化物的隔离沟槽附近是必要的，所以在这些区域中抑制刻面的技术是特别有意义的。 本文提出的一种这样的技术是使隔离沟槽与SiN对准，以在氧化物和预期外延生长的区域之间提供阻挡层。

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