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    Semiconductor device
    61.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12255206B2

    公开(公告)日：2025-03-18

    申请号：US17699724

    申请日：2022-03-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungil Park ,  Jae Hyun Park ,  Doyoung Choi ,  Youngmoon Choi ,  Daewon Ha

    IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

    Abstract: A semiconductor device includes: an active pattern extending in a first direction on a substrate; a first lower source/drain pattern and a second lower source/drain pattern provided on the active pattern and spaced apart from each other in the first direction; a first upper source/drain pattern provided on the first lower source/drain pattern; a second upper source/drain pattern provided on the second lower source/drain pattern; and a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction. The gate electrode includes an overlapping portion overlapping the active pattern in a third direction perpendicular to the first direction and the second direction. A length of the overlapping portion in the second direction is less than a length of the first lower source/drain pattern in the second direction.

    Semiconductor devices with stacked transistor structures
    62.
    发明授权
    Semiconductor devices with stacked transistor structures 有权

    公开(公告)号：US12166097B2

    公开(公告)日：2024-12-10

    申请号：US18390246

    申请日：2023-12-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungil Park ,  Jae Hyun Park ,  Kyungho Kim ,  Cheoljin Yun ,  Daewon Ha

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786

    Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. The first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

    Semiconductor devices with stacked transistor structures
    63.
    发明授权
    Semiconductor devices with stacked transistor structures 有权

    公开(公告)号：US11888044B2

    公开(公告)日：2024-01-30

    申请号：US17583314

    申请日：2022-01-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungil Park ,  Jae Hyun Park ,  Kyungho Kim ,  Cheoljin Yun ,  Daewon Ha

    IPC: H01L29/423 ,  H01L29/786 ,  H01L29/165 ,  H01L21/82

    CPC classification number: H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

    Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. the first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    64.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20220415931A1

    公开(公告)日：2022-12-29

    申请号：US17693883

    申请日：2022-03-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung Il Park ,  Jae Hyun Park ,  Do Young Choi ,  Yoshinao Harada ,  Dae Won Ha

    IPC: H01L27/12 ,  H01L21/822

    Abstract: A semiconductor device comprises a substrate, a first active pattern on the substrate and extending in a first direction, a second active pattern extending in the first direction spaced apart from the substrate, a gate electrode extending in a second direction surrounding the first and second active patterns, and a high dielectric film between the first and second active patterns and the gate electrode. The gate electrode includes first and second work function adjusting films surrounding the high dielectric film on the first and second active patterns, and a filling conductive film surrounding the first and second work function adjusting films. The first and second work function adjusting films include first and second work function conductive films, each of which includes a first metal film. A thickness of the first metal film of the first work function conductive film is greater than that of the second work function conductive film.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME
    65.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20220415906A1

    公开(公告)日：2022-12-29

    申请号：US17577120

    申请日：2022-01-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung Il Park ,  Jae Hyun Park ,  Min Gyu Kim ,  Do Young Choi ,  Dae Won Ha

    IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

    Abstract: A semiconductor memory device and a method for manufacturing the same. The semiconductor memory device may include a substrate, a first lower wire pattern and a first upper wire pattern stacked on the substrate, and spaced apart from each other; a second lower wire pattern and a second upper wire pattern stacked on the substrate, spaced apart from each other, and spaced apart from the first lower and upper wire patterns; a first gate line surrounding the first lower wire pattern and the first upper wire pattern; a second gate line surrounding the second lower wire pattern and the second upper wire pattern and spaced apart from the first gate line; a first lower source/drain area; a first upper source/drain area; and a first overlapping contact that electrically connects the first lower source/drain area, the first upper source/drain area and the second gate line to each other.

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