公开(公告)号：US20150085632A1

公开(公告)日：2015-03-26

申请号：US14037139

申请日：2013-09-25

Applicant: Seagate Technology LLC

Inventor： James Dillon Kiely ,  Jon D. Trantham

IPC: G11B27/36

CPC classification number: G11B5/41 ,  G11B5/40 ,  G11B5/455 ,  G11B5/607

Abstract: A heat generating component of a slider is energized at a predetermined frequency. The heat generating component changes a spacing between a medium and the slider. A temperature response proximate a media-facing surface of the slider is measured while the heating element is energized. Based on the measured temperature response, a determination is made as to whether the media-facing surface is contaminated. In response to determining that the media-facing surface is contaminated, remedial action is taken.

Abstract translation: 滑块的发热部件以预定的频率被激励。 发热组件改变介质和滑块之间的间距。 在加热元件通电时测量靠近滑块的面向媒体的表面的温度响应。 基于测量的温度响应，确定面向介质的表面是否被污染。 响应确定面向媒体的表面受到污染，采取补救措施。

公开(公告)号：US08949567B2

公开(公告)日：2015-02-03

申请号：US13777137

申请日：2013-02-26

Applicant: Seagate Technology LLC

Inventor： Antoine Khoueir ,  Jon D. Trantham ,  Kevin Gomez ,  Ara Patapoutian

IPC: G06F13/00 ,  G06F12/00

CPC classification number: G06F12/00 ,  G06F12/0238

Abstract: A plurality of addressable memory tiles each comprise one or more cross-point arrays. Each array comprises a plurality of non-volatile resistance-change memory cells. A controller is configured to couple to the array and to a host system. The controller is configured to perform receiving, from the host system, one or more data objects each having a size equal to a predetermined logical block size, and storing the one or more data objects in a corresponding integer number of one or more of the memory tiles.

Abstract translation: 多个可寻址存储器块各自包括一个或多个交叉点阵列。 每个阵列包括多个非易失性电阻变化存储单元。 控制器被配置为耦合到阵列和主机系统。 控制器被配置为执行从主机系统接收每个具有等于预定逻辑块大小的大小的一个或多个数据对象，并且将一个或多个数据对象存储在相应整数个存储器中的一个或多个存储器中 瓷砖。

公开(公告)号：US12125513B2

公开(公告)日：2024-10-22

申请号：US17726864

申请日：2022-04-22

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G11C11/22 ,  G11C7/10 ,  G11C17/12

CPC classification number: G11C11/2273 ,  G11C7/1039 ,  G11C11/2275 ,  G11C11/2297 ,  G11C17/12

Abstract: A system on chip (SOC) integrated circuit device having an incorporated ferroelectric memory configured to be selectively refreshed, or not, depending on different operational modes. The ferroelectric memory is formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer. The FMEs can include FeRAM, FeFET or FTJ constructions. A read/write circuit writes data to the FMEs and subsequently reads back data from the FMEs responsive to respective write and read signals supplied by a processor circuit of the SOC. A refresh circuit is selectively enabled in a first normal mode to refresh the FMEs after a read operation, and is selectively disabled in a second exception mode so that the FMEs are not refreshed after a read operation. The FMEs can be used as a main memory, a cache, a buffer, an OTP, a keystore, etc.

公开(公告)号：US11996144B2

公开(公告)日：2024-05-28

申请号：US17840779

申请日：2022-06-15

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G11C11/56 ,  G11C11/22

CPC classification number: G11C11/5657 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2273 ,  G11C11/2275

Abstract: A non-volatile memory (NVM) is formed of memory cells each having multiple ferroelectric memory elements (FMEs). Each FME stores data in relation to an electrical polarity of a recording layer formed of ferroelectric or anti-ferroelectric material. Each multi-FME memory cell is coupled to a set of external control lines activated by a control circuit in a selected order to perform program and/or read operations upon the FMEs. The FMEs may share a nominally identical construction or may have different constructions. Data are programmed and written responsive to the respective program/read responses of the FMEs. Constructions can include ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs). The NVM may form a portion of a data storage device, such as a solid-state drive (SSD).

公开(公告)号：US20230305972A1

公开(公告)日：2023-09-28

申请号：US17704553

申请日：2022-03-25

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Steven Scott Williams ,  Paul M. Wiggins ,  Thomas V. Spencer

IPC: G06F13/16 ,  G06F9/448 ,  G06F9/30

CPC classification number: G06F13/1668 ,  G06F13/1663 ,  G06F9/4498 ,  G06F9/30101

Abstract: An apparatus may include a memory device, a memory controller, or both that can communicate via memory standard interfaces. However, the memory device may have physical memory that does not comply with the memory standard by itself. Disclosed herein are solutions that allow various non-standard types of memory, or emerging memory, to be utilized via a host, microprocessor, or memory controller that implements the interface standard. For example, by utilizing a command converter at the microprocessor and a tunneling register at the memory device, a microprocessor can send commands to the memory device by writing them to the tunneling register, which can then be processed at the memory device for operations to be performed with the non-standard or emerging memory.

公开(公告)号：US11599577B2

公开(公告)日：2023-03-07

申请号：US16597911

申请日：2019-10-10

Applicant: Seagate Technology LLC

Inventor： Lijuan Zhong ,  Krishnan Subramanian ,  Mehmet Fatih Erden ,  Jon D. Trantham

IPC: G06F16/00 ,  G06F16/901 ,  G06N3/08 ,  G06F16/22

Abstract: Features are detected from a sensor signal via a deep-learning network or other feature engineering methods in an edge processing node. Machine-learned metadata is created that describes the features, and a hash is created with the machine-learned metadata. The sensor signal is stored as a content object at the edge processing node, the object being keyed with the hash at, the edge processing node.

公开(公告)号：US20220350739A1

公开(公告)日：2022-11-03

申请号：US17730920

申请日：2022-04-27

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Praveen Viraraghavan ,  John W. Dykes ,  Ian J. Gilbert ,  Sangita Shreedharan Kalarickal ,  Matthew J. Totin ,  Mohamad El-Batal ,  Darshana H. Mehta

IPC: G06F12/0802 ,  G06F3/06

Abstract: Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.

公开(公告)号：US11449238B2

公开(公告)日：2022-09-20

申请号：US16948984

申请日：2020-10-08

Applicant: Seagate Technology LLC

Inventor： Riyan A. Mendonsa ,  Brett R. Herdendorf ,  Jon D. Trantham ,  Krishnan Subramanian ,  John E. Moon ,  Hemant Mane

IPC: G06F3/06 ,  G06F11/34

Abstract: A data storage system can provide low cost and optimized performance with a cartridge housing multiple separate data storage devices and each of the data storage devices being concurrently engaged by a device player. The device player may have a processor configured to analyze mechanical performance of each data storage device and data performance of data resident in each data storage device.

公开(公告)号：US20210272983A1

公开(公告)日：2021-09-02

申请号：US17084940

申请日：2020-10-30

Applicant: Seagate Technology LLC

Inventor： Ian J. Gilbert ,  Steven D. Granz ,  Jon D. Trantham

IPC: H01L27/11597 ,  H01L27/24 ,  H01L45/00 ,  H01L27/1159 ,  H01L29/51 ,  H01L29/78

Abstract: A memory device has ferroelectric memory cells arranged into a three-dimensional (3D) structure. Each ferroelectric memory cell has a ferroelectric layer adapted to provide non-volatile storage of data. In some cases, each ferroelectric memory cell is arranged as a ferroelectric field effect transistor (FeFET) comprising a source region, a drain region, and a control gate region, the control gate region comprising the ferroelectric layer. In other cases, each ferroelectric memory cell is arranged as a ferroelectric tunnel junction (FTJ) comprising opposing conductive electrode layers between which the ferroelectric layer and a tunnel junction layer are contactingly disposed. The ferroelectric layer may be formed of HfO2, ZrO2, Hf1-xZxO2, etc. The tunnel barrier layer may be formed of Al2O3, MgO, SrTiO3, etc. The memory can be used as a substitute for DRAM, a main memory in a data storage device, a data cache, etc.

公开(公告)号：US10861490B1

公开(公告)日：2020-12-08

申请号：US16538180

申请日：2019-08-12

Applicant: Seagate Technology LLC

Inventor： Mark A. Gaertner ,  Jon D. Trantham ,  Vidur Parkash ,  Kevin N. Dao

IPC: G11B5/54 ,  G11B5/55 ,  G06F15/78 ,  G06F3/06

Abstract: A data storage device including an interface, a first actuator, a second actuator, an auxiliary controller, and a primary controller. The auxiliary controller is configured to control positioning of the second actuator. The primary controller is configured to control positioning of the first actuator. The primary controller is communicatively coupled between the interface and the auxiliary controller.