公开(公告)号：US07394720B2

公开(公告)日：2008-07-01

申请号：US11560746

申请日：2006-11-16

申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

IPC分类号： G11C8/00

CPC分类号： G06F12/02 ,  G11C7/1078 ,  G11C7/109

摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

摘要翻译： 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

公开(公告)号：US07376041B2

公开(公告)日：2008-05-20

申请号：US11024272

申请日：2004-12-27

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G11C7/00 ,  G11C7/10

CPC分类号： G11C7/22 ,  G11C7/1066

摘要： A semiconductor memory device includes a memory cell array to store data; a data input portion to output data to the memory cell array in response to a write control signal; a data output portion to output data from the memory cell array in response to a read control signal; a data I/O gate to transmit data outputted from the data input portion to the memory cell array in response to the write control signal, and transmitting data outputted from the memory cell array to the data output portion in response to the read control signal; and a data I/O controller to generate the read control signal and the write control signal having a smaller minimum cycle time than a minimum cycle time of the read control signal. The semiconductor memory device has an improved operation performance compared to one having a low operation frequency within an operable frequency range.

摘要翻译： 半导体存储器件包括用于存储数据的存储单元阵列; 数据输入部分，用于响应写控制信号将数据输出到存储单元阵列; 数据输出部分，用于响应于读取控制信号从存储单元阵列输出数据; 数据I / O门，用于响应于写控制信号将从数据输入部分输出的数据发送到存储单元阵列;以及响应于读控制信号将从存储单元阵列输出的数据发送到数据输出部分; 以及数据I / O控制器，用于产生具有比所读取的控制信号的最小周期时间更小的最小周期时间的读取控制信号和写入控制信号。 与在可操作频率范围内具有低工作频率的半导体存储器件相比，具有改进的操作性能。

公开(公告)号：US07366822B2

公开(公告)日：2008-04-29

申请号：US10840268

申请日：2004-05-07

申请人： Jin-Seok Kwak ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Sang-Bo Lee ,  Min-Sang Park ,  Chul-Soo Kim

发明人： Jin-Seok Kwak ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Sang-Bo Lee ,  Min-Sang Park ,  Chul-Soo Kim

IPC分类号： G06F12/00 ,  G11C8/00

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C11/4082 ,  G11C11/4087

摘要： A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.

摘要翻译： 半导体存储器件包括多个存储体。 数据路径可以被划分为读取数据路径和写入数据路径，因此并行处理写入和读取命令是可能的。 半导体存储器件可以包括地址库缓冲器，地址缓冲器，列预解码器和/或解码器。 半导体存储器件可以在一个时钟周期内开始执行存储体中的写入命令，并且在随后的时钟周期开始执行读取命令，因此总线效率增加和/或写入读取时间减少 。

公开(公告)号：US20070206428A1

公开(公告)日：2007-09-06

申请号：US11612800

申请日：2006-12-19

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Woong Shin ,  Ho-Young Song

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Woong Shin ,  Ho-Young Song

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.

摘要翻译： 提供了一种高速双倍或正交数据速率接口半导体器件及其方法。 用于高速数据传输的发射机（例如，数据传输半导体器件）发送第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和 第二组（字节）数据。 发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。 接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。 接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。 此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。

公开(公告)号：US07205799B2

公开(公告)日：2007-04-17

申请号：US11225915

申请日：2005-09-13

申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Joon Hwang ,  Ho-Young Song ,  Ho-Kyong Lee ,  Woo-Jin Lee

发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Joon Hwang ,  Ho-Young Song ,  Ho-Kyong Lee ,  Woo-Jin Lee

IPC分类号： H03K3/00

CPC分类号： H03F3/45

摘要： We describe an input buffer having a stabilized operating point and an associated method. An input buffer may include a first differential amplifying unit to generate a first output signal having a first operating point and a second differential amplifying unit to generate a second output signal having a second operating point. An output control circuit varies respective weights of the first and second output signals responsive to an output control signal. The first differential amplifying unit may operate responsive to a reference voltage and an input voltage signal. The second differential amplifying unit may operate responsive to the reference voltage and the input voltage signal. The first operating point may be relatively higher than the second operating point.

摘要翻译： 我们描述具有稳定的工作点和相关方法的输入缓冲器。 输入缓冲器可以包括第一差分放大单元，用于产生具有第一工作点的第一输出信号和第二差分放大单元，以产生具有第二工作点的第二输出信号。 响应于输出控制信号，输出控制电路改变第一和第二输出信号的各个权重。 第一差分放大单元可以响应于参考电压和输入电压信号而进行操作。 第二差分放大单元可以响应于参考电压和输入电压信号而工作。 第一工作点可以相对高于第二工作点。

公开(公告)号：US07187615B2

公开(公告)日：2007-03-06

申请号：US10943514

申请日：2004-09-17

申请人： Min-Sang Park ,  Yu-Lim Lee ,  Seong-Jin Jang

发明人： Min-Sang Park ,  Yu-Lim Lee ,  Seong-Jin Jang

IPC分类号： G11C8/00

CPC分类号： G11C8/12

摘要： A method for activating a word line segment of a semiconductor memory selected based on a row address provided to the memory can include activating a first word line segment selected by a row address and a command type and avoiding activating a second word line segment selected by the row address. Related devices are also disclosed.

摘要翻译： 用于激活基于提供给存储器的行地址选择的半导体存储器的字线段的方法可以包括激活由行地址和命令类型选择的第一字线段，并且避免激活由第二字线段选择的第二字线段 行地址。 还公开了相关设备。

公开(公告)号：US20060226868A1

公开(公告)日：2006-10-12

申请号：US11402123

申请日：2006-04-11

申请人： Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

发明人： Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

IPC分类号： H03K19/003

CPC分类号： H03K19/0005

摘要： Provided is a semiconductor device capable of controlling an on-die-termination (ODT) circuit and an off-chip-driver (OCD) circuit and a control method used by the semiconductor device. The semiconductor device includes a control code generation unit generating a control code in response to a control signal, an addition unit adding an adjustment code to the control code to produce an adjusted control code, and an ODT circuit, wherein an impedance of the ODT circuit is adjusted in response to the adjusted control code. The semiconductor device can adjust the control code more precisely by adding or subtracting the adjustment code to or from the control code. Accordingly, the impedance of an OCD circuit or ODT circuit can be adjusted more precisely.

摘要翻译： 提供了能够控制芯片上终端（ODT）电路和芯片外驱动器（OCD）电路的半导体器件以及由半导体器件使用的控制方法。 半导体器件包括响应于控制信号产生控制代码的控制代码生成单元，向控制代码添加调整代码以产生调整后的控制代码的加法单元和ODT电路，其中ODT电路的阻抗 根据调整后的控制代码进行调整。 半导体器件可以通过向或从控制代码添加或减去调整代码来更精确地调整控制代码。 因此，可以更精确地调整OCD电路或ODT电路的阻抗。

公开(公告)号：US20060066364A1

公开(公告)日：2006-03-30

申请号：US11225915

申请日：2005-09-13

申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Sang-Joon Hwang ,  Ho-Young Song ,  Ho-Kyong Lee ,  Woo-Jin Lee

发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Sang-Joon Hwang ,  Ho-Young Song ,  Ho-Kyong Lee ,  Woo-Jin Lee

IPC分类号： H03B1/00

CPC分类号： H03F3/45

摘要： We describe an input buffer having a stabilized operating point and an associated method. An input buffer may include a first differential amplifying unit to generate a first output signal having a first operating point and a second differential amplifying unit to generate a second output signal having a second operating point. An output control circuit varies respective weights of the first and second output signals responsive to an output control signal. The first differential amplifying unit may operate responsive to a reference voltage and an input voltage signal. The second differential amplifying unit may operate responsive to the reference voltage and the input voltage signal. The first operating point may be relatively higher than the second operating point.

摘要翻译： 我们描述具有稳定的工作点和相关方法的输入缓冲器。 输入缓冲器可以包括：第一差分放大单元，用于产生具有第一工作点的第一输出信号和第二差分放大单元，以产生具有第二工作点的第二输出信号。 响应于输出控制信号，输出控制电路改变第一和第二输出信号的各个权重。 第一差分放大单元可以响应于参考电压和输入电压信号而进行操作。 第二差分放大单元可以响应于参考电压和输入电压信号而工作。 第一工作点可以相对高于第二工作点。

公开(公告)号：US20050174858A1

公开(公告)日：2005-08-11

申请号：US11024272

申请日：2004-12-27

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G11C11/407 ,  G11C5/00 ,  G11C7/22 ,  G11C11/40 ,  G11C11/409

CPC分类号： G11C7/22 ,  G11C7/1066

摘要： A semiconductor memory device includes a memory cell array to store data; a data input portion to output data to the memory cell array in response to a write control signal; a data output portion to output data from the memory cell array in response to a read control signal; a data I/O gate to transmit data outputted from the data input portion to the memory cell array in response to the write control signal, and transmitting data outputted from the memory cell array to the data output portion in response to the read control signal; and a data I/O controller to generate the read control signal and the write control signal having a smaller minimum cycle time than a minimum cycle time of the read control signal. The semiconductor memory device has an improved operation performance compared to one having a low operation frequency within an operable frequency range.

摘要翻译： 半导体存储器件包括用于存储数据的存储单元阵列; 数据输入部分，用于响应写控制信号将数据输出到存储单元阵列; 数据输出部分，用于响应于读取控制信号从存储单元阵列输出数据; 数据I / O门，用于响应于写控制信号将从数据输入部分输出的数据发送到存储单元阵列;以及响应于读控制信号将从存储单元阵列输出的数据发送到数据输出部分; 以及数据I / O控制器，用于产生具有比所读取的控制信号的最小周期时间更小的最小周期时间的读取控制信号和写入控制信号。 与在可操作频率范围内具有低工作频率的半导体存储器件相比，具有改进的操作性能。

公开(公告)号：US06850110B2

公开(公告)日：2005-02-01

申请号：US10108276

申请日：2002-03-27

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G11C5/14 ,  H02M3/07 ,  G06F7/64

CPC分类号： H02M3/073 ,  H02M2003/075

摘要： A voltage generating circuit and method thereof for preventing a current from flowing from a voltage generating node to a pumping node in transiting of the circuit from an active operation to a pre-charge operation are provided. The voltage generating circuit comprises a pre-charge circuit for pre-charging a pumping node and a voltage transmitting control node during a pre-charge operation; a voltage pumping circuit for pumping a signal at the pumping node during an active operation; a voltage transmitting circuit for transmitting the signal from the pumping node to a voltage generating node in response to a signal at the voltage transmitting control node during the active operation; and a countercurrent preventing circuit for varying the signal at the voltage transmitting control node based on the signal at the pumping node during the pre-charge operation and for preventing a current from flowing between the pumping node and the voltage transmitting control node during the active operation.

摘要翻译： 提供一种电压产生电路及其方法，用于防止电流从电压产生节点流向泵送节点，以将电路从有源操作转移到预充电操作。 电压产生电路包括用于在预充电操作期间预充电泵浦节点和电压发送控制节点的预充电电路; 用于在主动操作期间泵送泵送节点处的信号的电压泵浦电路; 电压发送电路，用于在主动操作期间响应于电压发送控制节点处的信号将信号从泵送节点发送到电压产生节点; 以及逆流防止电路，用于在预充电操作期间基于泵送节点处的信号来改变电压发送控制节点处的信号，并且用于在主动操作期间防止在泵送节点和电压发送控制节点之间流动的电流 。