公开(公告)号：US5721172A

公开(公告)日：1998-02-24

申请号：US759242

申请日：1996-12-02

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/82 ,  H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/31053

摘要： A method for forming, without dishing, a planarized aperture fill layer within an aperture within a substrate. There is first provided a substrate having an aperture formed therein. There is then formed upon the substrate and within the aperture a conformal aperture fill layer, where the conformal aperture fill layer is thicker than the depth of the aperture. There is then formed upon the conformal aperture fill layer a conformal polish stop layer having a lower planar region of the conformal polish stop layer where the conformal aperture fill layer is formed within the aperture. The conformal polish stop layer and the conformal aperture fill layer are then planarized through a first chemical mechanical polish (CMP) planarizing method until there is reached the lower planar region of the conformal polish stop layer, while simultaneously forming a patterned polish stop layer and a partially chemical mechanical polish (CMP) planarized aperture fill layer. The patterned polish stop layer is then employed as a etch mask to form an etched partially chemical mechanical polish (CMP) planarized aperture fill layer with a protrusion over the aperture, where the height of the protrusion compensates for a dish which would otherwise form when the etched partially chemical mechanical polish (CMP) planarized aperture fill layer is planarized through a second chemical mechanical polish (CMP) method to form a planarized aperture fill layer within the aperture.

摘要翻译： 一种用于在衬底内的孔内形成平面化孔径填充层的方法。 首先设置有在其中形成有孔的基板。 然后在基底上并且在孔内形成保形孔填充层，其中保形孔填充层比孔的深度更厚。 然后在保形孔填充层上形成具有保形抛光停止层的下平面区域的共形抛光停止层，其中保形孔填充层形成在孔内。 然后通过第一化学机械抛光（CMP）平面化方法将保形抛光停止层和保形孔填充层平坦化，直到达到保形抛光停止层的下平面区域，同时形成图案化抛光停止层和 部分化学机械抛光（CMP）平面化孔径填充层。 然后将图案化的抛光停止层用作蚀刻掩模以形成蚀刻的部分化学机械抛光（CMP）平坦化的孔填充层，该孔在孔上方具有突起，其中突起的高度补偿了否则当 蚀刻的部分化学机械抛光（CMP）平面化孔径填充层通过第二化学机械抛光（CMP）方法平坦化，以在孔内形成平坦化的孔填充层。

公开(公告)号：US06458689B2

公开(公告)日：2002-10-01

申请号：US09818714

申请日：2001-03-28

申请人： Chen-Hua Yu ,  Syun-Ming Jang ,  Tsu Shih ,  Anthony Yen ,  Jih-Chuyng Twu

发明人： Chen-Hua Yu ,  Syun-Ming Jang ,  Tsu Shih ,  Anthony Yen ,  Jih-Chuyng Twu

IPC分类号： H01L214763

CPC分类号： H01L21/0276 ,  H01L21/31144 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/7684 ,  Y10S438/97

摘要： A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a dielectric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.

摘要翻译： 在化学机械抛光介质层平坦化工艺之后和用于接触的导电层的化学机械抛光之前，在电介质层上形成保护性（SiON或PE-Ox）电介质抗反射涂层（DARC）的方法或 通过插塞形成。 电介质层被化学机械抛光，从而在电介质层中形成微细结构。 本发明的保护性SiON或PE-OX DARC层形成在电介质层上，由此保护性SiON或PE-OX DARC层填充在微细凹槽中。 在其保护层和电介质层中蚀刻第一开口。 导电层形成在保护层上并填充第一开口。 导电层被化学机械抛光以从保护层上方移除导电层并形成填充第一开口的互连。 使用保护性SiON或PE-OX DARC层作为CMP阻挡层，从而防止电介质层中的微细纹。

公开(公告)号：US06444371B1

公开(公告)日：2002-09-03

申请号：US09377541

申请日：1999-08-19

申请人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

发明人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

IPC分类号： G03F900

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

摘要翻译： 描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。 本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。 本发明适用于用于形成现代高密度，多级集成电路的所有方法，并且不受所形成的层数或使用的材料的影响。 在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

公开(公告)号：US6020249A

公开(公告)日：2000-02-01

申请号：US891088

申请日：1997-07-10

申请人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： G03F9/00 ,  H01L23/544 ,  H01L23/48

CPC分类号： G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A method for forming alignment marks are disclosed for performing photoalignment after chemical-mechanical polishing (CMP). A trench is first formed in a silicon substrate and then alignment marks are formed at the bottom of the trench. The aspect ratio of the trench is selected to be so low that the dishing of the CMP pad can be prevented from reaching into the trench to damage the alignment marks therein. A trench structure is also provided whereby the alignment marks can be protected from the abrasive action of the CMP. Steps subsequent to the CMP can therefore proceed unimpeded with the presence of undamaged alignment marks.

公开(公告)号：US5972798A

公开(公告)日：1999-10-26

申请号：US86775

申请日：1998-05-29

申请人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

发明人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  Y10S438/942

摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

摘要翻译： 描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。 本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。 本发明适用于用于形成调制解调器高密度多电平集成电路的所有方法，而不受所形成的层数或使用的材料的影响。 在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

公开(公告)号：US07153197B2

公开(公告)日：2006-12-26

申请号：US10140728

申请日：2002-05-07

申请人： Tsu Shih ,  Sa-Na Lee ,  Syun-Ming Jang ,  Chi-Weng Chung

发明人： Tsu Shih ,  Sa-Na Lee ,  Syun-Ming Jang ,  Chi-Weng Chung

IPC分类号： B24B1/00 ,  C23G1/02

CPC分类号： H01L21/3212 ,  B24B37/042 ,  H01L21/31683 ,  Y10S134/902

摘要： A method for removing a metal oxide overlayer over a target polishing surface in conjunction with a chemical mechanical polishing (CMP) process to improve polishing uniformity including providing a substrate target polishing surface having a layer of an oxide of a metal overlying said metal to be chemically mechanically polished; removing the layer of an oxide of the metal using an oxide removal solution prior to performing a CMP process with an abrasive slurry; and, polishing the target polishing surface according to an a CMP process with an abrasive slurry including at least one of an oxidizer and a complexing agent.

公开(公告)号：US5923996A

公开(公告)日：1999-07-13

申请号：US867312

申请日：1997-06-02

申请人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L23/544 ,  H01L21/46 ,  H01L21/301 ,  H01L21/78

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A method is disclosed for forming alignment marks at the outer perimeter of wafers where they are not susceptible to much damage during chemical-mechanical polishing (CMP) process. Complete protection is provided by recessing the alignment mark into the substrate by etching. Recess etching is accomplished at the same time the isolation trenches are followed to delineate device areas. Thus, alignment marks are provided with a protective recess without extra steps. Furthermore, by forming alignment marks at the outer perimeter of the wafer, productivity is improved by providing maximum usage of wafer area for integrated circuits.

摘要翻译： 公开了一种用于在晶片的外周边形成对准标记的方法，其中它们在化学机械抛光（CMP）工艺期间不会受到很大的损害。 通过蚀刻将对准标记凹入衬底来提供完整的保护。 在同时完成凹槽蚀刻，同时遵循隔离沟以描绘器件区域。 因此，对准标记设置有保护凹槽而没有额外的步骤。 此外，通过在晶片的外周形成对准标记，通过提供用于集成电路的晶片面积的最大使用来提高生产率。

公开(公告)号：US06686284B2

公开(公告)日：2004-02-03

申请号：US10072244

申请日：2002-02-06

申请人： Chi-Wei Chung ,  Tung-Ching Tseng ,  Tsu Shih ,  Syun-Ming Jang

发明人： Chi-Wei Chung ,  Tung-Ching Tseng ,  Tsu Shih ,  Syun-Ming Jang

IPC分类号： H01L2100

CPC分类号： H01L21/3212 ,  B24B37/32 ,  B24B55/02 ,  H01L21/31053

摘要： A chemical mechanical polishing apparatus that is equipped with a chilled retaining ring and a method for using the apparatus are described. The retaining ring is mounted therein a heat transfer means such as a metal tube and flowing therethrough a heat exchanging fluid for carrying away heat from the wafer mounted in the retaining ring, resulting in a temperature reduction in the slurry solution that contacts the wafer. The present invention apparatus and method therefore reduces the delamination problem for low k dielectric materials during polishing and the wafer scratching problem.

摘要翻译： 描述了配备有冷冻保持环的化学机械抛光装置和使用该装置的方法。 保持环安装有诸如金属管的传热装置，并在其中流过用​​于从安装在保持环中的晶片携带热量的热交换流体，导致与晶片接触的浆液中的温度降低。 因此，本发明的装置和方法减少了抛光期间低k电介质材料和晶片划伤问题的分层问题。

公开(公告)号：US09647066B2

公开(公告)日：2017-05-09

申请号：US13454960

申请日：2012-04-24

申请人： Chang-Shen Lu ,  Chih-Tang Peng ,  Tai-Chun Huang ,  Pei-Ren Jeng ,  Hao-Ming Lien ,  Yi-Hung Lin ,  Tze-Liang Lee ,  Syun-Ming Jang

发明人： Chang-Shen Lu ,  Chih-Tang Peng ,  Tai-Chun Huang ,  Pei-Ren Jeng ,  Hao-Ming Lien ,  Yi-Hung Lin ,  Tze-Liang Lee ,  Syun-Ming Jang

IPC分类号： H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/20

CPC分类号： H01L29/10 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/6681 ,  H01L29/785

摘要： A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality of semiconductor fins. The active FinFET and the dummy FinFET are laterally spaced from each other by a spacing that is related to the fin pitch of the active FinFET.

公开(公告)号：US09029260B2

公开(公告)日：2015-05-12

申请号：US13161701

申请日：2011-06-16

申请人： Chun Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Syun-Ming Jang

发明人： Chun Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/511 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括形成具有多个第一开口的图案化电介质层。 该方法包括在图案化的介电层上形成导电衬垫层，导电衬垫层部分填充第一开口。 该方法包括在第一开口之外的导电衬垫层的部分上形成沟槽掩模层，从而形成多个第二开口，其中一部分形成在第一开口上。 该方法包括在第一开口中沉积导电材料以形成多个通孔，并且在第二开口中形成多个金属线。 该方法包括去除沟槽掩模层。