公开(公告)号：US06458689B2

公开(公告)日：2002-10-01

申请号：US09818714

申请日：2001-03-28

申请人： Chen-Hua Yu ,  Syun-Ming Jang ,  Tsu Shih ,  Anthony Yen ,  Jih-Chuyng Twu

发明人： Chen-Hua Yu ,  Syun-Ming Jang ,  Tsu Shih ,  Anthony Yen ,  Jih-Chuyng Twu

IPC分类号： H01L214763

CPC分类号： H01L21/0276 ,  H01L21/31144 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/7684 ,  Y10S438/97

摘要： A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a dielectric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.

摘要翻译： 在化学机械抛光介质层平坦化工艺之后和用于接触的导电层的化学机械抛光之前，在电介质层上形成保护性（SiON或PE-Ox）电介质抗反射涂层（DARC）的方法或 通过插塞形成。 电介质层被化学机械抛光，从而在电介质层中形成微细结构。 本发明的保护性SiON或PE-OX DARC层形成在电介质层上，由此保护性SiON或PE-OX DARC层填充在微细凹槽中。 在其保护层和电介质层中蚀刻第一开口。 导电层形成在保护层上并填充第一开口。 导电层被化学机械抛光以从保护层上方移除导电层并形成填充第一开口的互连。 使用保护性SiON或PE-OX DARC层作为CMP阻挡层，从而防止电介质层中的微细纹。

公开(公告)号：US06228760B1

公开(公告)日：2001-05-08

申请号：US09263563

申请日：1999-03-08

申请人： Chen-Hua Yu ,  Syun-Ming Jang ,  Tsu Shih ,  Anthony Yen ,  Jih-Churng Twu

发明人： Chen-Hua Yu ,  Syun-Ming Jang ,  Tsu Shih ,  Anthony Yen ,  Jih-Churng Twu

IPC分类号： H01L214763

CPC分类号： H01L21/0276 ,  H01L21/31144 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/7684 ,  Y10S438/97

摘要： A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a di electric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.

摘要翻译： 在化学机械抛光介电层平坦化工艺之后和用于接触的导电层的化学机械抛光之前，在二电层上形成保护性（SiON或PE-Ox）电介质抗反射涂层（DARC）的方法 或通过插塞形成。 电介质层被化学机械抛光，从而在电介质层中形成微细结构。 本发明的保护性SiON或PE-OX DARC层形成在电介质层上，由此保护性SiON或PE-OX DARC层填充在微细凹槽中。 在其保护层和电介质层中蚀刻第一开口。 导电层形成在保护层上并填充第一开口。 导电层被化学机械抛光以从保护层上方移除导电层并形成填充第一开口的互连。 使用保护性SiON或PE-OX DARC层作为CMP阻挡层，从而防止电介质层中的微细纹。

公开(公告)号：US06444371B1

公开(公告)日：2002-09-03

申请号：US09377541

申请日：1999-08-19

申请人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

发明人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

IPC分类号： G03F900

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

摘要翻译： 描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。 本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。 本发明适用于用于形成现代高密度，多级集成电路的所有方法，并且不受所形成的层数或使用的材料的影响。 在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

公开(公告)号：US6020249A

公开(公告)日：2000-02-01

申请号：US891088

申请日：1997-07-10

申请人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： G03F9/00 ,  H01L23/544 ,  H01L23/48

CPC分类号： G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A method for forming alignment marks are disclosed for performing photoalignment after chemical-mechanical polishing (CMP). A trench is first formed in a silicon substrate and then alignment marks are formed at the bottom of the trench. The aspect ratio of the trench is selected to be so low that the dishing of the CMP pad can be prevented from reaching into the trench to damage the alignment marks therein. A trench structure is also provided whereby the alignment marks can be protected from the abrasive action of the CMP. Steps subsequent to the CMP can therefore proceed unimpeded with the presence of undamaged alignment marks.

公开(公告)号：US5972798A

公开(公告)日：1999-10-26

申请号：US86775

申请日：1998-05-29

申请人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

发明人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  Y10S438/942

摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

摘要翻译： 描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。 本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。 本发明适用于用于形成调制解调器高密度多电平集成电路的所有方法，而不受所形成的层数或使用的材料的影响。 在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

公开(公告)号：US5923996A

公开(公告)日：1999-07-13

申请号：US867312

申请日：1997-06-02

申请人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L23/544 ,  H01L21/46 ,  H01L21/301 ,  H01L21/78

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A method is disclosed for forming alignment marks at the outer perimeter of wafers where they are not susceptible to much damage during chemical-mechanical polishing (CMP) process. Complete protection is provided by recessing the alignment mark into the substrate by etching. Recess etching is accomplished at the same time the isolation trenches are followed to delineate device areas. Thus, alignment marks are provided with a protective recess without extra steps. Furthermore, by forming alignment marks at the outer perimeter of the wafer, productivity is improved by providing maximum usage of wafer area for integrated circuits.

摘要翻译： 公开了一种用于在晶片的外周边形成对准标记的方法，其中它们在化学机械抛光（CMP）工艺期间不会受到很大的损害。 通过蚀刻将对准标记凹入衬底来提供完整的保护。 在同时完成凹槽蚀刻，同时遵循隔离沟以描绘器件区域。 因此，对准标记设置有保护凹槽而没有额外的步骤。 此外，通过在晶片的外周形成对准标记，通过提供用于集成电路的晶片面积的最大使用来提高生产率。

公开(公告)号：US20060027932A1

公开(公告)日：2006-02-09

申请号：US11240216

申请日：2005-09-30

申请人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Syun-Ming Jang ,  Chenming Hu

发明人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Syun-Ming Jang ,  Chenming Hu

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76846

摘要： Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.

摘要翻译： 复合ALD形成的扩散阻挡层。 在优选实施例中，复合导电层由扩散阻挡层和/或由电介质中的镶嵌开口衬底的原子层沉积（ALD）形成的低电阻金属层组成，用作扩散阻挡和/或粘附改善。 优选的复合扩散阻挡层是通过ALD在开口上依次形成的双氮化钛层或双氮化钽层，三层层状的钽，氮化钽和富钽的氮化物，或钽，氮化钽和钽。

公开(公告)号：US06559040B1

公开(公告)日：2003-05-06

申请号：US09421517

申请日：1999-10-20

申请人： Chen-Hua Yu ,  Chung-Long Chang ,  Syun-Ming Jang

发明人： Chen-Hua Yu ,  Chung-Long Chang ,  Syun-Ming Jang

IPC分类号： H01L21302

CPC分类号： H01L21/3212 ,  H01L21/28035

摘要： The process of polishing the top surface of a polysilicon gate electrode often results in significant loss of material before adequate smoothness is achieved. This problem is overcome in the present invention by laying down a thin layer of a dielectric on the surface of the polysilicon prior to the application of CMP. This provides a sacrificial layer that facilitates the polishing operation and results in a polysilicon surface that is both very smooth and achievable with minimum loss of polysilicon.

摘要翻译： 抛光多晶硅栅电极的顶表面的过程通常在达到足够的平滑度之前导致材料的显着损失。 在本发明中通过在施加CMP之前在多晶硅的表面上放置介电层的薄层来克服该问题。 这提供了促进抛光操作的牺牲层，并且导致多晶硅表面非常平滑并且可以以最小的多晶硅损失实现。

公开(公告)号：US06500753B2

公开(公告)日：2002-12-31

申请号：US09838209

申请日：2001-04-20

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Jih-Churng Twu ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Jih-Churng Twu ,  Chen-Hua Yu

IPC分类号： H01L218238

CPC分类号： H01L21/7684 ,  H01L21/76838 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention teaches the addition of copper lines, these copper lines to be added to isolated copper lines or to selected copper lines within a collection of copper lines. The invention also teaches the addition of copper end caps to isolated copper lines or to selected copper lines within a collection of copper lines. The invention further teaches the widening of copper lines for isolated copper lines or selected copper lines within a collection of copper lines.

摘要翻译： 本发明教导了铜线的添加，这些铜线被添加到隔离铜线或铜线集合内的选定铜线。 本发明还教导了将铜端盖添加到铜线集合中的隔离铜线或铜线。 本发明进一步教导了铜线集合中用于隔离铜线或选定铜线的铜线的扩大。

公开(公告)号：US06245691B1

公开(公告)日：2001-06-12

申请号：US09086770

申请日：1998-05-29

申请人： Syun-Ming Jang ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L2131

CPC分类号： H01L21/02164 ,  C23C16/0218 ,  C23C16/0272 ,  C23C16/402 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/31662

摘要： A method for forming a silicon oxide dielectric layer within a microelectronics fabrication. There is first provided a silicon substrate layer employed within a microelectronics fabrication. There is then formed employing the silicon substrate a thermal silicon oxide layer through thermal oxidation of the silicon substrate layer. There is then formed upon the thermal silicon oxide layer a second silicon oxide layer formed through use of a thermal chemical vapor deposition (CVD) method employing ozone as an oxidant and tetraethylorthosilicate (TEOS) as a silicon source material. The thermal chemical vapor deposition (CVD) method also employs a reactor chamber pressure of from about 40 to about 80 torr. The second silicon oxide layer is formed with an attenuated surface sensitivity of the second silicon oxide layer with respect to the thermal silicon oxide layer. The method is particularly desirable when forming trench isolation regions within isolation trenches within silicon semiconductor substrates employed within integrated circuit microelectronics fabrications.

摘要翻译： 一种在微电子制造中形成氧化硅介电层的方法。 首先提供在微电子制造中使用的硅衬底层。 然后通过硅衬底层的热氧化形成硅衬底热硅氧化物层。 然后在热氧化硅层上形成第二氧化硅层，该第二氧化硅层通过使用以臭氧作为氧化剂的热化学气相沉积（CVD）方法和作为硅源材料的原硅酸四乙酯（TEOS）形成。 热化学气相沉积（CVD）方法也采用约40至约80托的反应室压力。 第二氧化硅层形成有相对于热氧化硅层的第二氧化硅层的衰减的表面灵敏度。 当在集成电路微电子学制造中使用的硅半导体衬底内的隔离沟槽内形成沟槽隔离区域时，该方法是特别需要的。