公开(公告)号：US5319223A

公开(公告)日：1994-06-07

申请号：US918057

申请日：1992-07-24

申请人： Shinobu Fujita ,  Takao Noda ,  Yasuo Ashizawa

发明人： Shinobu Fujita ,  Takao Noda ,  Yasuo Ashizawa

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/778 ,  H01L29/80

CPC分类号： H01L29/7783

摘要： A high electron mobility transistor (HEMT) comprises an InGaAs channel layer formed on a semi-insulating InP substrate via a buffer layer, and an n-type InA.iota.As electron supply layer formed on the channel layer via a spacer layer. On the electron supply layer, formed is an InGaA.iota.P Schottky contact layer, on which a Schottky gate electrode is formed. Source and drain electrodes are formed on the Schottky contact layer via an InGaAs ohmic contact layer, interposing the Schottky gate electrode therebetween. Thus, there is provided an InA.iota.As/InGaAs HEMT having a high gate breakdown voltage, and exhibiting a small variance of characteristics.

摘要翻译： 高电子迁移率晶体管（HEMT）包括通过缓冲层形成在半绝缘InP衬底上的InGaAs沟道层，以及通过间隔层形成在沟道层上的n型InAiAAsAs电子供给层。 在电子供给层上，形成有形成肖特基型栅电极的InGaA iota P肖特基接触层。 源极和漏极通过InGaAs欧姆接触层在肖特基接触层上形成，其间插入肖特基栅电极。 因此，提供了具有高栅极击穿电压并且表现出小的特性差异的InA iAAsAs / InGaAs HEMT。

公开(公告)号：US08243498B2

公开(公告)日：2012-08-14

申请号：US12884452

申请日：2010-09-17

申请人： Keiko Abe ,  Shinobu Fujita

发明人： Keiko Abe ,  Shinobu Fujita

IPC分类号： G11C11/00

CPC分类号： G11C14/009 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/21 ,  G11C14/0054 ,  G11C14/0081

摘要： According to one embodiment, a semiconductor integrated circuit includes first and second inverters, a first transistor which has a gate connected to a word line, a source connected to a first bit line, and a drain connected to an input terminal of the second inverter, a second transistor which has a gate connected to the word line, a source connected to a second bit line, and a drain connected to an input terminal of the first inverter, a first variable resistive element which has a first terminal connected to the drain of the first transistor, and a second terminal connected to an output terminal of the first inverter, and a second variable resistive element which has a first terminal connected to the drain of the second transistor, and a second terminal connected to an output terminal of the second inverter.

摘要翻译： 根据一个实施例，半导体集成电路包括第一和第二反相器，具有连接到字线的栅极的第一晶体管，连接到第一位线的源极和连接到第二反相器的输入端子的漏极， 第二晶体管，其具有连接到字线的栅极，连接到第二位线的源极和连接到第一反相器的输入端子的漏极;第一可变电阻元件，其具有连接到第一位线的漏极的第一端子 第一晶体管和连接到第一反相器的输出端的第二端子，以及第二可变电阻元件，其具有连接到第二晶体管的漏极的第一端子，以及连接到第二晶体管的输出端子的第二端子 逆变器。

公开(公告)号：US07558813B2

公开(公告)日：2009-07-07

申请号：US12143104

申请日：2008-06-20

申请人： Tetsufumi Tanamoto ,  Shinobu Fujita

发明人： Tetsufumi Tanamoto ,  Shinobu Fujita

IPC分类号： G06F7/58 ,  H01L29/772

CPC分类号： B82Y10/00 ,  G06F7/588 ,  H01L29/7888 ,  H04L9/0861

摘要： The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

公开(公告)号：US20080211540A1

公开(公告)日：2008-09-04

申请号：US12038807

申请日：2008-02-27

申请人： Shinobu Fujita

发明人： Shinobu Fujita

IPC分类号： H03K19/173

CPC分类号： H03K19/17748 ,  H03K19/1776 ,  H03K19/1778

摘要： According to some embodiments, an “excess-current programming method” on ZnCdS memory devices for FPGA applications is disclosed. an “excess-current programming method” can also be employed within a variety of other applications, including other memory devices having low On-resistance, such as, e.g., metal-oxide memory like Ti-oxide, Ni-oxide, W-oxide, Cu-oxide and so on. Embodiments of ZnCdS based devices (e.g., memory devices), FPGA elements incorporating the same and methods thereof for reconfigurable circuits can reduce area overhead, power overhead and/or latency (e.g., of FPGA), address a disturbance problem during logic operation, decrease an ON-resistance characteristic and/or obtain increased data retention.

摘要翻译： 根据一些实施例，公开了用于FPGA应用的ZnCdS存储器件上的“过电流编程方法”。 也可以在各种其他应用中使用“过电流编程方法”，包括具有低导通电阻的其它存储器件，例如诸如氧化钛，氧化镍，氧化钼的金属氧化物存储器 ，氧化铜等。 基于ZnCdS的器件（例如，存储器件），与其组合的FPGA元件及其可重构电路的方法的实施例可以减少面积开销，功率开销和/或等待时间（例如FPGA），解决逻辑运算期间的干扰问题，减少 导通电阻特性和/或获得增加的数据保留。

公开(公告)号：US07111029B2

公开(公告)日：2006-09-19

申请号：US10235827

申请日：2002-09-06

申请人： Shinobu Fujita ,  Ken Uchida ,  Ryuji Ohba ,  Junji Koga

发明人： Shinobu Fujita ,  Ken Uchida ,  Ryuji Ohba ,  Junji Koga

IPC分类号： G06F1/02

CPC分类号： H04L9/0861 ,  G06F7/588

摘要： A random number generating circuit can generate random numbers with high randomness, and can be made as a compact integrated circuit. The random number generating circuit includes an uncertain logic circuit having a flip-flop type logic circuit that gives digital output values not determined definitely by a digital input value, and an equalizing circuit having an exclusive OR operating circuit for equalizing appearance frequencies of “0” and “1” in the digital output values output from the uncertain logic circuit.

公开(公告)号：US07001787B2

公开(公告)日：2006-02-21

申请号：US10902301

申请日：2004-07-30

申请人： Tetsufumi Tanamoto ,  Satoshi Saito ,  Shinobu Fujita

发明人： Tetsufumi Tanamoto ,  Satoshi Saito ,  Shinobu Fujita

IPC分类号： H01L21/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  G11C13/025 ,  H01J9/025 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  Y10T428/256 ,  Y10T428/259

摘要： An electrode manufacturing method comprises: forming plural protruding portions on a surface of a substrate; introducing first particles having a size that changes according to heat, light, or a first solvent between said plural protruding portions; changing the size of the first particles by applying heat, light, or the first solvent to said first particles; and depositing an electrode material onto the surface of said substrate.

摘要翻译： 电极制造方法包括：在基板的表面上形成多个突出部分; 在所述多个突出部之间引入具有根据热，光或第一溶剂变化的尺寸的第一颗粒; 通过向所述第一颗粒施加热，光或第一溶剂来改变第一颗粒的尺寸; 以及将电极材料沉积到所述衬底的表面上。

公开(公告)号：US09003128B2

公开(公告)日：2015-04-07

申请号：US13234837

申请日：2011-09-16

申请人： Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

发明人： Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0897 ,  G06F12/123 ,  G06F2212/225 ,  Y02D10/13

摘要： According to an embodiment, in a cache system, the sequence storage stores sequence data in association with each piece of data to be stored in the volatile cache memory in accordance with the number of pieces of data stored in the nonvolatile cache memory that have been unused for a longer period of time than the data stored in the volatile cache memory or the number of pieces of data stored in the nonvolatile cache memory that have been unused for a shorter period of time than the data stored in the volatile cache memory. The controller causes the first piece of data to be stored in the nonvolatile cache memory in a case where it can be determined that the first piece of data has been unused for a shorter period of time than any piece of the data stored in the nonvolatile cache memory.

摘要翻译： 根据实施例，在高速缓存系统中，序列存储器根据存储在非易失性高速缓冲存储器中的数据的数量与已经被使用的非易失性高速缓冲存储器中存储的数据数量相关联地存储与要存储在易失性高速缓存存储器中的每条数据相关联 比存储在易失性高速缓冲存储器中的数据或存储在非易失性高速缓冲存储器中的数据的时间长于存储在易失性高速缓冲存储器中的数据的时间长于较短时间段的更长时间段。 在可以确定第一条数据已被使用的时间短于存储在非易失性高速缓冲存储器中的任何数据的时间段的情况下，控制器使得第一条数据被存储在非易失性高速缓冲存储器中 记忆。

公开(公告)号：US08716805B2

公开(公告)日：2014-05-06

申请号：US12237152

申请日：2008-09-24

申请人： Shinobu Fujita

发明人： Shinobu Fujita

IPC分类号： H01L27/00

CPC分类号： H01L27/0688 ,  H01L27/101

摘要： A complementary metal oxide semiconductor (CMOS) circuit having integrated functional devices such as nanowires, carbon nanotubes, magnetic memory cells, phase change memory cells, ferroelectric memory cells or the like. The functional devices are integrated with the CMOS circuit. The functional devices are bonded (e.g. by direct bonding, anodic bonding, or diffusion bonding) to a top surface of the CMOS circuit. The functional devices are fabricated and processed on a carrier wafer, and an attachment layer (e.g. SiO2) is deposited over the functional devices. Then, the CMOS circuit and attachment layer are bonded. The carrier wafer is removed (e.g. by etching). The functional devices remain attached to the CMOS circuit via the attachment layer. Apertures are etched through the attachment layer to provide a path for electrical connections between the CMOS circuit and the functional devices.

摘要翻译： 具有纳米线，碳纳米管，磁存储单元，相变存储单元，铁电存储单元等集成功能元件的互补金属氧化物半导体（CMOS）电路。 功能器件与CMOS电路集成。 功能器件通过例如直接接合，阳极结合或扩散接合来结合到CMOS电路的顶表面。 功能器件在载体晶片上制造和处理，并且在功能器件上沉积附着层（例如SiO 2）。 然后，连接CMOS电路和附着层。 移除载体晶片（例如通过蚀刻）。 功能器件通过附着层保持连接到CMOS电路。 孔径通过附着层蚀刻，以提供用于CMOS电路和功能器件之间的电连接的路径。

公开(公告)号：US20130031397A1

公开(公告)日：2013-01-31

申请号：US13421090

申请日：2012-03-15

申请人： Keiko Abe ,  Shinobu Fujita

发明人： Keiko Abe ,  Shinobu Fujita

IPC分类号： G06F1/32

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14

摘要： One embodiment provides an information processing apparatus including a processor; memory blocks; an internal voltage generator connected to the memory blocks; an input/output circuit connected to the memory blocks; switches each installed corresponding to the internal voltage generator, the input/output circuit, and the memory blocks, and configured to switch ON/OFF of the connection with a power source; a data register configured to store a data set that controls the ON/OFF of the switches; and a data management circuit configured to set the data set in the data register, wherein when a clock signal input to the processor is turned to OFF, the data management circuit generates a first type of the data set, which switches ON the switch connected to the internal voltage generator and switches OFF the switches connected to the memory blocks, and sets the first type of the data set in the data register.

摘要翻译： 一个实施例提供一种包括处理器的信息处理设备; 记忆块 连接到存储块的内部电压发生器; 连接到存储器块的输入/输出电路; 对应于内部电压发生器，输入/输出电路和存储器块的每个安装开关，并被配置为用电源来切换连接的ON / OFF; 数据寄存器，被配置为存储控制开关的ON / OFF的数据组; 以及数据管理电路，被配置为将数据集合设置在数据寄存器中，其中当输入到处理器的时钟信号变为OFF时，数据管理电路产生第一类型的数据组，其将接通的开关 内部电压发生器和断开连接到存储器块的开关，并将数据集的第一种类型设置在数据寄存器中。

公开(公告)号：US08239809B2

公开(公告)日：2012-08-07

申请号：US12504272

申请日：2009-07-16

申请人： Shinobu Fujita

发明人： Shinobu Fujita

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A 3-dimensional integrated circuit designing method includes forming a temporary layout region for an original integrated circuit on an XY plane, the plane being short in an X direction and long in a Y direction perpendicular to the X direction, dividing the temporary layout region into 2N (N is an integral number of not smaller than 2) or more subregions in the Y direction, configuring one block for every successive N subregions to prepare a plurality of blocks, and forming N layers of layout by alternately folding each of the blocks in the Y direction in units of one subregion to selectively set a kN-th (k is an integral number not less than 1) subregion and (kN+1)th subregion of each block to one of an uppermost layer and lowermost layer.

摘要翻译： 三维集成电路设计方法包括在XY平面上形成用于原始集成电路的临时布局区域，该平面在X方向上短并且在垂直于X方向的Y方向上长，将临时布局区域分成 2N（N是不小于2的整数）或更多个子区域，为每个连续的N个子区域配置一个块以准备多个块，并且通过交替地将每个块的每个块交替地折叠来形成N个层的布局 以一个子区域为单位的Y方向，选择性地将各块的kN（k为1以上的整数）子区域和（kN + 1）个子区域设置为最上层和最下层中的一个。