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    Forming ultra dense 3-D interconnect structures
    63.
    发明申请
    Forming ultra dense 3-D interconnect structures 审中-公开
    形成超密度3-D互连结构

    公开(公告)号：US20070161150A1

    公开(公告)日：2007-07-12

    申请号：US11322058

    申请日：2005-12-28

    申请人： Patrick Morrow

    发明人： Patrick Morrow

    IPC分类号： H01L21/00

    CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01327 ,  H01L2924/00

    摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include bonding at least one bond pad of a device side of a first substrate to at least one bond pad of a device side of a second substrate, forming at least one via to connect to at least one of an active feature and an interconnect structure disposed within the first substrate, and forming a reactive material on a surface of at least one of the active features.

    摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括将第一衬底的器件侧的至少一个焊盘焊接到第二衬底的器件侧的至少一个接合焊盘，形成至少一个通孔，以连接至活性特征和 布置在所述第一基板内的互连结构，以及在至少一个所述有源特征的表面上形成反应性材料。

    Method for making a dual damascene interconnect using a dual hard mask
    65.
    发明授权
    Method for making a dual damascene interconnect using a dual hard mask 有权
    使用双重硬掩模制作双镶嵌互连的方法

    公开(公告)号：US06872666B2

    公开(公告)日：2005-03-29

    申请号：US10289807

    申请日：2002-11-06

    申请人： Patrick Morrow

    发明人： Patrick Morrow

    IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/768

    CPC分类号： H01L21/76811 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/76813 ,  H01L21/76835 ,  H01L2221/1036

    摘要： An improved method of forming a semiconductor device is described. Initially, a structure is formed that includes first and second hard masking layers that cover a dielectric layer. A first part of the second hard masking layer and a first part of the first hard masking layer are etched to form an etched region within the hard mask that exposes a first portion of the dielectric layer. That etched region is filled with a sacrificial material. After etching through a second part of the second hard masking layer, the remainder of the sacrificial material is removed prior to subsequent processing.

    摘要翻译： 描述了一种形成半导体器件的改进方法。 最初，形成包括覆盖电介质层的第一和第二硬掩模层的结构。 蚀刻第二硬掩模层的第一部分和第一硬掩模层的第一部分以在硬掩模内形成暴露电介质层的第一部分的蚀刻区域。 该蚀刻区域填充有牺牲材料。 在蚀刻通过第二硬掩模层的第二部分之后，在随后的处理之前去除剩余的牺牲材料。

    Methods of making field effect transistor structure with partially isolated source/drain junctions
    66.
    发明授权
    Methods of making field effect transistor structure with partially isolated source/drain junctions 失效
    具有部分隔离的源极/漏极结的场效应晶体管结构的方法

    公开(公告)号：US06541343B1

    公开(公告)日：2003-04-01

    申请号：US09474836

    申请日：1999-12-30

    申请人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Robert S. McFadden

    发明人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Robert S. McFadden

    IPC分类号： H01L21336

    CPC分类号： H01L29/66628 ,  H01L29/0653 ,  H01L29/66636

    摘要： A microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type. In a further aspect of the invention, a process for forming a microelectronic structure, such as a MOSFET, having at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type includes forming a recess having a surface, forming a dielectric material over a portion of the surface of the recess, and back-filling the recess to form a source/drain terminal.

    摘要翻译： 微电子结构包括与第二导电类型的半导体材料的区域部分隔离的第一导电类型的至少一个源极/漏极端子。 在本发明的另一方面，用于形成诸如MOSFET的微电子结构的方法具有至少一个与第二导电类型的半导体材料的区域部分隔离的第一导电类型的源极/漏极端子，包括 形成具有表面的凹部，在所述凹部的所述表面的一部分上形成电介质材料，并且对所述凹部进行后填充以形成源极/漏极端子。

    Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure
    67.
    发明授权
    Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure 有权
    制造具有与支撑结构间隔开的双镶嵌互连的半导体器件的方法

    公开(公告)号：US06448177B1

    公开(公告)日：2002-09-10

    申请号：US09819881

    申请日：2001-03-27

    申请人： Patrick Morrow ,  Xiaorong Morrow

    发明人： Patrick Morrow ,  Xiaorong Morrow

    IPC分类号： H01L21331

    CPC分类号： H01L21/76808 ,  H01L21/76811 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76835 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device and an improved method for making it are described. The semiconductor device comprises a dual damascene interconnect that includes a conductive line. The device further includes a support structure that is spaced from the conductive line, and an insulating layer that is formed on the support structure and the conductive line. In the method for forming that device, a support structure is formed on a substrate, and an insulating layer is formed adjacent to it. Portions of the insulating layer are removed to form a via and a trench, which are filled with a conductive material to generate a dual damascene interconnect that includes a conductive line, wherein the conductive line is spaced from the support structure.

    摘要翻译： 对半导体装置及其制造方法进行说明。 该半导体器件包括包括导电线的双镶嵌互连。 该装置还包括与导电线隔开的支撑结构以及形成在支撑结构和导电线上的绝缘层。 在用于形成该器件的方法中，在衬底上形成支撑结构，并且在其附近形成绝缘层。 去除绝缘层的一部分以形成通孔和沟槽，沟槽填充有导电材料以产生包括导线的双镶嵌互连，其中导电线与支撑结构间隔开。