公开(公告)号：US08179713B2

公开(公告)日：2012-05-15

申请号：US12671162

申请日：2009-05-18

申请人： Yoshihiko Kanzawa ,  Satoru Mitani ,  Zhiqiang Wei ,  Takeshi Takagi

发明人： Yoshihiko Kanzawa ,  Satoru Mitani ,  Zhiqiang Wei ,  Takeshi Takagi

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2418 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： A nonvolatile memory element comprises a first electrode (103), a second electrode (105), and a resistance variable layer (104) which is provided between the first electrode and the second electrode, and is configured to reversibly switch an interelectrode resistance value which is a resistance value between the first electrode and the second electrode, in response to an interelectrode voltage which is an electric potential of the second electrode on the basis of the first electrode, the resistance variable layer includes an oxygen-deficient transition metal oxide, the first electrode side and the second electrode side have an asymmetric structure, a portion of the resistance variable layer which is located at the first electrode side and a portion of the resistance variable layer which is located at the second electrode side are each configured to be selectively placed into one of a low-resistance state and a high-resistance state, so as to attain a stable state in three or more different interelectrode resistance values, the stable state being a state in which the interelectrode resistance value is invariable regardless of a change in the interelectrode voltage within a specified range.

摘要翻译： 非易失性存储元件包括设置在第一电极和第二电极之间的第一电极（103），第二电极（105）和电阻变化层（104），并且被配置为可逆地切换电极间电阻值， 是第一电极和第二电极之间的电阻值，响应于基于第一电极的第二电极的电位的电极间电压，电阻变化层包括缺氧过渡金属氧化物， 第一电极侧和第二电极侧具有不对称结构，位于第一电极侧的电阻变化层的一部分和位于第二电极侧的电阻变化层的一部分分别构成为选择性地 放置成低电阻状态和高电阻状态之一，以达到三个或更多个差异的稳定状态 出现电极间电阻值，稳定状态是不管电极间电压在规定范围内的变化如何，电极间电阻值不变的状态。

公开(公告)号：US20110110143A1

公开(公告)日：2011-05-12

申请号：US13001840

申请日：2010-04-09

申请人： Yoshihiko Kanzawa ,  Takeshi Takagi

发明人： Yoshihiko Kanzawa ,  Takeshi Takagi

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0011 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2213/34 ,  G11C2213/79

摘要： Provided is a programming method for improving the retention characteristics of information in a variable resistance nonvolatile memory element. The method includes: a first writing process of applying a first voltage V1 having a first polarity to set the variable resistance nonvolatile storage element to a low resistance state LR indicating first logic information (S01); a second writing process of applying a second voltage V2 having a second polarity different from the first polarity to set the variable resistance nonvolatile storage element to a first high resistance state HR1 (S02); and a partial write process of applying a third voltage V3 having the first polarity so as to set the variable resistance layer to a second high resistance state HR2 indicating second logic information different from the first logic information (S05). Here, |V3|

摘要翻译： 提供了一种用于改善可变电阻非易失性存储元件中的信息的保持特性的编程方法。 该方法包括：施加具有第一极性的第一电压V1的第一写入处理将可变电阻非易失性存储元件设置为指示第一逻辑信息的低电阻状态LR（S01）; 第二写入处理，施加具有与第一极性不同的第二极性的第二电压V2，以将可变电阻非易失性存储元件设置为第一高电阻状态HR1（S02）; 以及施加具有第一极性的第三电压V3以便将可变电阻层设置为指示与第一逻辑信息不同的第二逻辑信息的第二高电阻状态HR2的部分写入处理（S05）。 这里，| V3 | <| V1 |，HR1，HR2，LR中的电阻值依次较大。

公开(公告)号：US07473967B2

公开(公告)日：2009-01-06

申请号：US10558671

申请日：2004-05-31

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

IPC分类号： H01L27/088

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/78687

摘要： A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherein a semiconductor forming the channel region has a lattice strain.

摘要翻译： 根据本发明的半导体器件包括：第一绝缘层（11）; 第一主体部分（13），其包括形成在所述第一绝缘层上的岛状半导体; 包括形成在所述第一绝缘层上的岛状半导体的第二主体部分（14） 形成在第一绝缘层上以互连第一主体部分和第二主体部分的脊形连接部分（15）; 由连接部的长度方向的至少一部分形成的通道区域（15a）; 形成为覆盖沟道区域的周边的栅极电极（18），其间插入有第二绝缘层; 形成为在第一主体部分上延伸的源极区域和在第一主体部分和沟道区域之间的连接部分的一部分; 以及形成为在第二主体部分上延伸的漏极区域和在第二主体部分和沟道区域之间的连接部分的一部分，其中形成沟道区域的半导体具有晶格应变。

公开(公告)号：US06852602B2

公开(公告)日：2005-02-08

申请号：US10298000

申请日：2002-01-30

申请人： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Katsuya Nozawa ,  Minoru Kubo ,  Yoshihiro Hara ,  Takeshi Takagi ,  Takahiro Kawashima

发明人： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Katsuya Nozawa ,  Minoru Kubo ,  Yoshihiro Hara ,  Takeshi Takagi ,  Takahiro Kawashima

IPC分类号： H01L21/205 ,  H01L29/15 ,  H01L29/24 ,  H01L29/737 ,  H01L29/80 ,  H01L21/331

CPC分类号： H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L29/155 ,  H01L29/1608 ,  H01L29/7378 ,  H01L29/802

摘要： A multi-layer film 10 is formed by stacking a Si1-x1-y1Gex1Cy1 layer (0≦x1 y2) having a high Ge mole fraction, e.g., a Si0.2Ge0.8 layer 12. In this manner, the range in which the multi-layer film serves as a SiGeC layer with C atoms incorporated into lattice sites extends to high degrees in which a Ge mole fraction is high.

摘要翻译： 通过层叠具有小Ge摩尔分数的Si1-x1-y1Gex1Cy1层（0 <= x1 <1和0 y2），例如Si0.2Ge0.8层 以这种方式，多层膜用作结合到晶格点中的C原子的SiGeC层的范围延伸到Ge摩尔分数高的高度。

公开(公告)号：US06455364B1

公开(公告)日：2002-09-24

申请号：US09526686

申请日：2000-03-15

申请人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

发明人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

IPC分类号： H01L218249

CPC分类号： H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

摘要翻译： 在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极层。 通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电极开口的范围覆盖集电极层和器件隔离的一部分。 在位于集电体开口内部的半导体基板的一部分上形成作为外部基底的第二导电类型的半导体层，同时在半导体衬底中形成与外部基底相同的导电类型的防漏层。 因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

公开(公告)号：US08094482B2

公开(公告)日：2012-01-10

申请号：US12529466

申请日：2008-10-28

申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Ken Kawai ,  Kazuhiko Shimakawa

发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Ken Kawai ,  Kazuhiko Shimakawa

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2211/5646 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

摘要： A nonvolatile memory apparatus and a nonvolatile data storage medium of the present invention, including nonvolatile memory elements each of which changes its resistance in response to electric pulses applied, comprises a first write circuit for performing first write in which a first electric pulse is applied to the nonvolatile memory element to switch a resistance value of the nonvolatile memory element from a first resistance value to a second resistance value and a second electric pulse which is opposite in polarity to the first electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from the second resistance value to the first resistance value.

摘要翻译： 本发明的非易失性存储装置和非易失性数据存储介质，包括各自根据施加的电脉冲改变其电阻的非易失性存储元件，包括用于执行第一写入的第一写入电路，其中施加第一电脉冲到 将非易失性存储元件的电阻值从第一电阻值切换到与第一电脉冲极性相反的第二电阻值和第二电脉冲的非易失性存储元件施加到非易失性存储元件，以将电阻 非易失性存储元件的值从第二电阻值到第一电阻值。

公开(公告)号：US20100110766A1

公开(公告)日：2010-05-06

申请号：US12524313

申请日：2008-02-22

申请人： Zhiqiang Wei ,  Kazuhiko Shimakawa ,  Takeshi Takagi ,  Yoshikazu Katoh

发明人： Zhiqiang Wei ,  Kazuhiko Shimakawa ,  Takeshi Takagi ,  Yoshikazu Katoh

IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C7/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/1021

摘要： A nonvolatile memory apparatus comprises a memory array (102) including plural first electrode wires (WL) formed to extend in parallel with each other within a first plane; plural second electrode wires (BL) formed to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plural first electrode wires; and nonvolatile memory elements (11) which are respectively provided at three-dimensional cross points between the first electrode wires and the second electrode wires, the elements each having a resistance variable layer whose resistance value changes reversibly in response to a current pulse supplied between an associated first electrode wire and an associated second electrode wire; and a first selecting device (13) for selecting the first electrode wires, and further comprises voltage restricting means (15) provided within or outside the memory array, the voltage restricting means being connected to the first electrode wires, for restricting a voltage applied to the first electrode wires to a predetermined upper limit value or less; wherein plural nonvolatile memory elements of the nonvolatile memory elements are connected to one first electrode wire connecting the first selecting device to the voltage restricting means.

摘要翻译： 非易失性存储装置包括存储器阵列（102），其包括形成为在第一平面内彼此平行延伸的多个第一电极线（WL） 多个第二电极线（BL），其形成为在与第一平面平行的第二平面内彼此平行延伸并且三维地交叉所述多个第一电极线; 和非易失性存储元件（11），其分别设置在第一电极线和第二电极线之间的三维交叉点处，每个元件具有电阻变化层，其电阻值响应于在 相关联的第一电极线和相关联的第二电极线; 以及用于选择所述第一电极线的第一选择装置（13），并且还包括设置在所述存储器阵列内或外的电压限制装置（15），所述电压限制装置连接到所述第一电极线，用于限制施加到 所述第一电极线达到预定的上限值以下; 其中所述非易失性存储元件的多个非易失性存储元件连接到将所述第一选择装置连接到所述电压限制装置的一个第一电极线。

公开(公告)号：US07916516B2

公开(公告)日：2011-03-29

申请号：US12524313

申请日：2008-02-22

申请人： Zhiqiang Wei ,  Kazuhiko Shimakawa ,  Takeshi Takagi ,  Yoshikazu Katoh

发明人： Zhiqiang Wei ,  Kazuhiko Shimakawa ,  Takeshi Takagi ,  Yoshikazu Katoh

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/1021

摘要： A nonvolatile memory apparatus comprises a memory array (102) including plural first electrode wires (WL) formed to extend in parallel with each other within a first plane; plural second electrode wires (BL) formed to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plural first electrode wires; and nonvolatile memory elements (11) which are respectively provided at three-dimensional cross points between the first electrode wires and the second electrode wires, the elements each having a resistance variable layer whose resistance value changes reversibly in response to a current pulse supplied between an associated first electrode wire and an associated second electrode wire; and a first selecting device (13) for selecting the first electrode wires, and further comprises voltage restricting means (15) provided within or outside the memory array, the voltage restricting means being connected to the first electrode wires, for restricting a voltage applied to the first electrode wires to a predetermined upper limit value or less; wherein plural nonvolatile memory elements of the nonvolatile memory elements are connected to one first electrode wire connecting the first selecting device to the voltage restricting means.

摘要翻译： 非易失性存储装置包括存储器阵列（102），其包括形成为在第一平面内彼此平行延伸的多个第一电极线（WL） 多个第二电极线（BL），其形成为在与第一平面平行的第二平面内彼此平行延伸并且三维地交叉所述多个第一电极线; 和非易失性存储元件（11），其分别设置在第一电极线和第二电极线之间的三维交叉点处，每个元件具有电阻变化层，其电阻值响应于在 相关联的第一电极线和相关联的第二电极线; 以及用于选择所述第一电极线的第一选择装置（13），并且还包括设置在所述存储器阵列内或外的电压限制装置（15），所述电压限制装置连接到所述第一电极线，用于限制施加到 所述第一电极线达到预定的上限值以下; 其中所述非易失性存储元件的多个非易失性存储元件连接到将所述第一选择装置连接到所述电压限制装置的一个第一电极线。

公开(公告)号：US20100014343A1

公开(公告)日：2010-01-21

申请号：US12529466

申请日：2008-10-28

申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Ken Kawai ,  Kazuhiko Shimakawa

发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Ken Kawai ,  Kazuhiko Shimakawa

IPC分类号： G11C11/00 ,  G11C11/416

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2211/5646 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

摘要： [Objective] A nonvolatile memory apparatus and a nonvolatile data storage medium of the present invention, including nonvolatile memory elements each of which changes its resistance in response to electric pulses applied, comprises a first write circuit (106) for performing first write in which a first electric pulse is applied to the nonvolatile memory element to switch a resistance value of the nonvolatile memory element from a first resistance value to a second resistance value and a second electric pulse which is opposite in polarity to the first electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from the second resistance value to the first resistance value; and a second write circuit (108) for performing second write in which a third electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from a third resistance value to a fourth resistance value and a fourth electric pulse which is identical in polarity to the third electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from the fourth resistance value to a fifth resistance value.

摘要翻译： [目的]本发明的非易失性存储装置和非易失性数据存储介质，包括响应于施加的电脉冲改变其电阻的非易失性存储元件，包括用于执行第一写入的第一写入电路（106），其中 将第一电脉冲施加到非易失性存储元件，以将非易失性存储元件的电阻值从第一电阻值切换到第二电阻值，并将与第一电脉冲极性相反的第二电脉冲施加到非易失性存储元件 存储元件，用于将非易失性存储元件的电阻值从第二电阻值切换到第一电阻值; 以及第二写入电路（108），用于执行第二写入，其中第三电脉冲被施加到非易失性存储元件，以将非易失性存储元件的电阻值从第三电阻值切换到第四电阻值和第四电脉冲 将与第三电脉冲相同的极性相加到非易失性存储元件，以将非易失性存储元件的电阻值从第四电阻值切换到第五电阻值。

公开(公告)号：US09251898B2

公开(公告)日：2016-02-02

申请号：US13983855

申请日：2012-02-07

申请人： Koji Katayama ,  Takeshi Takagi

发明人： Koji Katayama ,  Takeshi Takagi

IPC分类号： G11C13/00 ,  H01L27/10 ,  H01L27/102 ,  H01L49/02 ,  H01L45/00 ,  H01L27/24 ,  G11C29/50

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/004 ,  G11C29/50008 ,  G11C2013/0045 ,  G11C2013/0083 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2418 ,  H01L28/20 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

摘要： A method for programming a nonvolatile memory element includes: decreasing a resistance value of a variable resistance element in an initial state, by applying an initialization voltage pulse to a series circuit in which a load resistor having a first resistance value is connected in series with the variable resistance element and a MSM diode; applying, after the decreasing, a write voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a second resistance value lower than the first resistance value; and applying, after the decreasing, an erase voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a third resistance value lower than the first resistance value.

摘要翻译： 一种用于非易失性存储元件的编程方法包括：通过向串联电路施加初始化电压脉冲来降低初始状态下的可变电阻元件的电阻值，其中具有第一电阻值的负载电阻器与 可变电阻元件和MSM二极管; 在可变电阻元件的电阻值变为低于第一电阻值的第二电阻值之后，在减小之后向串联电路施加写入电压脉冲; 以及在所述可变电阻元件的电阻值变为低于所述第一电阻值的第三电阻值之后，在所述减小之后向所述串联电路施加擦除电压脉冲。